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LoongArch: Add hardware breakpoints/watchpoints support
authorQing Zhang <zhangqing@loongson.cn>
Sat, 25 Feb 2023 07:52:57 +0000 (15:52 +0800)
committerHuacai Chen <chenhuacai@loongson.cn>
Sat, 25 Feb 2023 14:12:17 +0000 (22:12 +0800)
commitedffa33c7bb5a73e90c754c7a497162b77d7c55f
tree64292d0bc9301134eaeafd6a02977cc9e8913fd6
parent35c94fab6eee72d60d9cd8d1e6e43e1f77b1dce2
LoongArch: Add hardware breakpoints/watchpoints support

Use perf framework to manage hardware instruction and data breakpoints.

LoongArch defines hardware watchpoint functions for instruction fetch
and memory load/store operations. After the software configures hardware
watchpoints, the processor hardware will monitor the access address of
the instruction fetch and load/store operation, and trigger an exception
of the watchpoint when it meets the conditions set by the watchpoint.

The hardware monitoring points for instruction fetching and load/store
operations each have a register for the overall configuration of all
monitoring points, a register for recording the status of all monitoring
points, and four registers required for configuration of each watchpoint
individually.

Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
arch/loongarch/Kconfig
arch/loongarch/include/asm/hw_breakpoint.h [new file with mode: 0644]
arch/loongarch/include/asm/loongarch.h
arch/loongarch/include/asm/processor.h
arch/loongarch/include/asm/switch_to.h
arch/loongarch/kernel/Makefile
arch/loongarch/kernel/hw_breakpoint.c [new file with mode: 0644]
arch/loongarch/kernel/process.c
arch/loongarch/kernel/traps.c