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arm64: Add MIDR encoding for HiSilicon Taishan CPUs
authorHanjun Guo <hanjun.guo@linaro.org>
Tue, 5 Mar 2019 13:40:57 +0000 (21:40 +0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 19 Mar 2019 14:55:10 +0000 (14:55 +0000)
commitefd00c722ca855745fcc35a7e6675b5a782a3fc8
treed560bc695fa0a43795df25e5fb602371036346a6tree | snapshot
parentc82fd1e6bd55ecc001e610e5484e292a7d8a39fccommit | diff
arm64: Add MIDR encoding for HiSilicon Taishan CPUs

Adding the MIDR encodings for HiSilicon Taishan v110 CPUs,
which is used in Kunpeng ARM64 server SoCs. TSV110 is the
abbreviation of Taishan v110.

Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/include/asm/cputype.h diff | blob | history
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