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(parent: 934fe5f) | patch
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
authorChen-Yu Tsai <wens@csie.org>
Tue, 24 Mar 2015 17:22:08 +0000 (01:22 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 25 Mar 2015 18:46:41 +0000 (11:46 -0700)
commitf1017969661dd33ead5ba7c3f4a0793c6611441a
treeb4e6aec3ce3765f5c6692abec131768ffa8110bctree | snapshot
parent934fe5f48ae52841f8a5f5e0411147a8ccd171c1commit | diff
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6

The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
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