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ACPICA: MADT: Add RISC-V INTC interrupt controller
authorSunil V L <sunilvl@ventanamicro.com>
Wed, 5 Apr 2023 13:40:12 +0000 (15:40 +0200)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 6 Apr 2023 18:29:11 +0000 (20:29 +0200)
commitf2ca92d08325b8d4668a6b3ee4b3d5622b75b952
tree9fd4b9e81cf5b138e321631fbd8a4c9c4c0f8296tree | snapshot
parent520d4a0ee5b6d9c7a1258ace6caa13a94ac35ef8commit | diff
ACPICA: MADT: Add RISC-V INTC interrupt controller

ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015

The ECR to add RISC-V INTC interrupt controller is approved by
the UEFI forum and will be available in the next revision of
the ACPI specification.

Link: https://github.com/acpica/acpica/commit/bd6d1ae1
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
include/acpi/actbl2.h diff | blob | history
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