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target/hppa: sar register allows only 5 bits on 32-bit CPU
authorHelge Deller <deller@gmx.de>
Mon, 16 Oct 2023 12:43:18 +0000 (14:43 +0200)
committerRichard Henderson <richard.henderson@linaro.org>
Tue, 7 Nov 2023 02:49:33 +0000 (18:49 -0800)
commitf3618f59f3559eae69c34e0fe621685614b4350d
tree31d98f6c9caf73a3a5057bc4d5c606d45f811006
parentf13bf343ccdb7df14233133f42670e1b16bb6b20
target/hppa: sar register allows only 5 bits on 32-bit CPU

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>
target/hppa/translate.c