[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class

[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class

I was expecting this to be a nfc but Silvermont seems to be setup a little differently:

// A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;

So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct.

Differential Revision: https://reviews.llvm.org/D52740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343670 91177308-0d34-0410-b5e6-96231b3b80d8