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author	Sirish Pande <sirishrp@gmail.com>
	Wed, 16 May 2018 15:36:52 +0000 (15:36 +0000)
committer	Sirish Pande <sirishrp@gmail.com>
	Wed, 16 May 2018 15:36:52 +0000 (15:36 +0000)
commit	f9deb984807b7d5f76974aa40a35c7377faf56f0
tree	7a70251b8f5691f555f18874210ed6f816565265	tree \| snapshot
parent	46a30b98c29af57d5543dd9c3bdbc2c1ab6beaad	commit \| diff

[AArch64] Gangup loads and stores for pairing.

Keep loads and stores together (target defines how many loads
and stores to gang up), such that it will help in pairing
and vectorization.

Differential Revision https://reviews.llvm.org/D46477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332482 91177308-0d34-0410-b5e6-96231b3b80d8

external/llvm

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include/llvm/CodeGen/TargetLowering.h		diff \| blob \| history
lib/CodeGen/SelectionDAG/SelectionDAG.cpp		diff \| blob \| history
lib/CodeGen/TargetLoweringBase.cpp		diff \| blob \| history
lib/Target/AArch64/AArch64ISelLowering.cpp		diff \| blob \| history
test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-memcpy-inline.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-variadic-aapcs.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-virtual_base.ll		diff \| blob \| history
test/CodeGen/AArch64/mergestores_noimplicitfloat.ll		diff \| blob \| history
test/CodeGen/ARM/memcpy-inline.ll		diff \| blob \| history