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(parent: 8c95e17) | patch
phy: cadence: Sierra: Add PHY PCS common register configurations
authorSwapnil Jakhade <sjakhade@cadence.com>
Thu, 23 Dec 2021 06:01:29 +0000 (07:01 +0100)
committerVinod Koul <vkoul@kernel.org>
Mon, 27 Dec 2021 11:05:09 +0000 (16:35 +0530)
commitfa10517211f72f9480677796b97cbe5a8f3a298f
treedb89745fbb7a5229ff7920841527120f7dacbc56tree | snapshot
parent8c95e1722689f1b1e63a6206acba2b6200ed7864commit | diff
phy: cadence: Sierra: Add PHY PCS common register configurations

Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
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