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(parent: 1c6b2e4) | patch
tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Thu, 2 Feb 2023 12:04:26 +0000 (13:04 +0100)
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Wed, 8 Feb 2023 08:58:08 +0000 (09:58 +0100)
commitfa581531ffdc94ba18da6ec0c566bece57a60a85
tree0ac4200794cba419db7a30139e92b6d0422f70e4tree | snapshot
parent1c6b2e4b794d460a16a7f94cf6a7d6864f708be1commit | diff
tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT

DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
tests/tcg/tricore/Makefile.softmmu-target diff | blob | history
tests/tcg/tricore/macros.h diff | blob | history
tests/tcg/tricore/test_insert.S [new file with mode: 0644] blob
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