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AMDGPU: Fix ubsan error
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 23 Jan 2020 19:10:04 +0000 (14:10 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Thu, 23 Jan 2020 20:05:47 +0000 (15:05 -0500)
commitfac9941e57013127593a47e02e7e88f56c9be2a4
tree93eeed338202458238fc9a1ca92d2cb738041b20tree | snapshot
parentb749af6a1ff45434011278c3ba765a41f0ee02f2commit | diff
AMDGPU: Fix ubsan error

Since register classes go up to 1024, 32 elements, all masks bits are
needed and a 32-bit shift by 32 is illegal. We didn't have any
instructions theoretically using a 32 element VGPR before
d1dbb5e4718a8f845abf0783513a33a55429470b
llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp diff | blob | history
external/llvm-project
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