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drm/i915: Enable edp psr error interrupts on hsw
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Apr 2018 22:00:23 +0000 (15:00 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Fri, 20 Apr 2018 21:28:13 +0000 (14:28 -0700)
commitfc34044248b611ea3f8b6e55b4ed404192a4f295
tree0bcbbab2a88874a7677c94770ae58400fb88dbea
parentc4c252590951704947d216a2565ee9dec21f704d
drm/i915: Enable edp psr error interrupts on hsw

The definitions for the error register should be valid on bdw/skl too,
but there we haven't even enabled DE_MISC handling yet.

Somewhat confusing the the moved register offset on bdw is only for
the _CTL/_AUX register, and that _IIR/IMR stayed where they have been
on bdw.

v2: Fixes from Ville.

v3: From DK
 * Rebased on drm-tip
 * Removed BDW IIR bit definition, looks like an unintentional change that
should be in the following patch.

v4: From DK
 * Don't mask REG_WRITE.

References: bspec/11974 [SRD Interrupt Bit Definition DevHSW]
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180405220023.9449-1-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h