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drm/i915: Correctly map DBUF slices to pipes
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Sun, 2 Feb 2020 23:06:30 +0000 (01:06 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 5 Feb 2020 17:22:11 +0000 (19:22 +0200)
commitff2cd8635e41e0cb375ae2ad1ec05728fcd56c49
tree495fdc267689e6212aea9f6fc2bc1f3386058c95
parent0f0f9aeee3347fa76e4c5c376867b64240a541b7
drm/i915: Correctly map DBUF slices to pipes

Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.

v2:
    - Remove unneeded braces
    - Stop using macro for DBuf assignments as
      it seems to reduce readability.

v3: Start using enabled slices mask in dev_priv

v4: Renamed "enabled_slices" used in dev_priv
    to "enabled_dbuf_slices_mask"(Matt Roper)

v5: - Removed redundant parameters from
      intel_get_ddb_size function.(Matt Roper)
    - Made i915_possible_dbuf_slices static(Matt Roper)
    - Renamed total_width into total_width_in_range
      so that it now reflects that this is not
      a total pipe width but the one in current
      dbuf slice allowed range for pipe.(Matt Roper)
    - Removed 4th pipe for ICL in DBuf assignment
      table(Matt Roper)
    - Fixed wrong DBuf slice in DBuf table for TGL
      (Matt Roper)
    - Added comment regarding why we currently not
      using pipe ratio for DBuf assignment for ICL

v6: - Changed u32 to unsigned int in
      icl_get_first_dbuf_slice_offset function signature
      (Ville Syrjälä)
    - Changed also u32 to u8 in dbuf slice mask structure
      (Ville Syrjälä)
    - Switched from DBUF_S1_BIT to enum + explicit
      BIT(DBUF_S1) access(Ville Syrjälä)
    - Switched to named initializers in DBuf assignment
      arrays(Ville Syrjälä)
    - DBuf assignment arrays now use autogeneration tool
      from
      https://patchwork.freedesktop.org/series/70493/
      to avoid typos.
    - Renamed i915_find_pipe_conf to *_compute_dbuf_slices
      (Ville Syrjälä)
    - Changed platforms ordering in skl_compute_dbuf_slices
      to be from newest to oldest(Ville Syrjälä)

v7: - Now ORing assigned DBuf slice config always with DBUF_S1
      because slice 1 has to be constantly powered on.
      (Ville Syrjälä)

v8: - Added pipe_name for neater printing(Ville Syrjälä)
    - Renamed width_before_pipe to width_before_pipe_in_range,
      to better reflect that now all the calculations are happening
      inside DBuf range allowed by current pipe configuration mask
      (Ville Syrjälä)
    - Shortened FIXME comment message, regarding constant ORing with
      DBUF_S1(Ville Syrjälä)
    - Added .dbuf_mask named initializer to pipe assignment array
      (Ville Syrjälä)
    - Edited pipe assignment array to use only single DBuf slice
      for gen11 single pipe configurations, until "pipe ratio"
      thing is finally sorted out(Ville Syrjälä)
    - Removed unused parameter crtc_state for now(Ville Syrjälä)
      from icl/tgl_compute_dbuf_slices function

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200202230630.8975-7-stanislav.lisovskiy@intel.com
drivers/gpu/drm/i915/intel_pm.c