While temp3 could simply be initialized with tcg_constant_i32,
the renaming makes the purpose clearer.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
uint32_t op2;
uint32_t off10;
int32_t r1, r2;
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
case OPC2_32_BO_CACHEA_WI_CIRC:
case OPC2_32_BO_CACHEA_W_CIRC:
case OPC2_32_BO_CACHEA_I_CIRC:
case OPC2_32_BO_CACHEA_WI_CIRC:
case OPC2_32_BO_CACHEA_W_CIRC:
case OPC2_32_BO_CACHEA_I_CIRC:
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_A_BR:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_A_BR:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_A_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_A_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_B_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_ST_B_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_ST_B_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_ST_B_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
break;
case OPC2_32_BO_ST_D_BR:
CHECK_REG_PAIR(r1);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
break;
case OPC2_32_BO_ST_DA_BR:
CHECK_REG_PAIR(r1);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_H_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_ST_H_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_ST_H_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_ST_H_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_Q_BR:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
break;
case OPC2_32_BO_ST_Q_BR:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
case OPC2_32_BO_ST_Q_CIRC:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
case OPC2_32_BO_ST_Q_CIRC:
tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_ST_W_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_W_BR:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_W_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_ST_W_CIRC:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
uint32_t op2;
uint32_t off10;
int r1, r2;
uint32_t op2;
uint32_t off10;
int r1, r2;
-
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LD_A_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_LD_A_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_B_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
break;
case OPC2_32_BO_LD_B_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
break;
case OPC2_32_BO_LD_B_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
break;
case OPC2_32_BO_LD_B_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_BU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_LD_BU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_LD_BU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
break;
case OPC2_32_BO_LD_BU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
break;
case OPC2_32_BO_LD_D_BR:
CHECK_REG_PAIR(r1);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
break;
case OPC2_32_BO_LD_DA_BR:
CHECK_REG_PAIR(r1);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_rem_tl(temp, temp, temp2);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_H_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
break;
case OPC2_32_BO_LD_H_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
break;
case OPC2_32_BO_LD_H_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
break;
case OPC2_32_BO_LD_H_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_HU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_LD_HU_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_LD_HU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_LD_HU_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_Q_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
break;
case OPC2_32_BO_LD_Q_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
case OPC2_32_BO_LD_Q_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
case OPC2_32_BO_LD_Q_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_LD_W_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_LD_W_BR:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_LD_W_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
break;
case OPC2_32_BO_LD_W_CIRC:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
uint32_t op2;
uint32_t off10;
int r1, r2;
uint32_t op2;
uint32_t off10;
int r1, r2;
-
- TCGv temp, temp2, temp3;
+ TCGv temp, temp2, t_off10;
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
r1 = MASK_OP_BO_S1D(ctx->opcode);
r2 = MASK_OP_BO_S2(ctx->opcode);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp = tcg_temp_new();
temp2 = tcg_temp_new();
- temp3 = tcg_const_i32(off10);
+ t_off10 = tcg_constant_i32(off10);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
break;
case OPC2_32_BO_LDMST_CIRC:
gen_ldmst(ctx, r1, temp2);
break;
case OPC2_32_BO_LDMST_CIRC:
gen_ldmst(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_SWAP_W_BR:
gen_swap(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAP_W_BR:
gen_swap(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAP_W_CIRC:
gen_swap(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAP_W_CIRC:
gen_swap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_CMPSWAP_W_BR:
gen_cmpswap(ctx, r1, temp2);
break;
case OPC2_32_BO_CMPSWAP_W_BR:
gen_cmpswap(ctx, r1, temp2);
break;
case OPC2_32_BO_CMPSWAP_W_CIRC:
gen_cmpswap(ctx, r1, temp2);
break;
case OPC2_32_BO_CMPSWAP_W_CIRC:
gen_cmpswap(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
case OPC2_32_BO_SWAPMSK_W_BR:
gen_swapmsk(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAPMSK_W_BR:
gen_swapmsk(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAPMSK_W_CIRC:
gen_swapmsk(ctx, r1, temp2);
break;
case OPC2_32_BO_SWAPMSK_W_CIRC:
gen_swapmsk(ctx, r1, temp2);
- gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
+ gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);