+int
+gen6_pipeline_estimate_query_size(const struct ilo_3d_pipeline *p,
+ const struct ilo_query *q)
+{
+ int size;
+
+ ILO_DEV_ASSERT(p->dev, 6, 7.5);
+
+ switch (q->type) {
+ case PIPE_QUERY_OCCLUSION_COUNTER:
+ size = GEN6_PIPE_CONTROL__SIZE;
+ if (ilo_dev_gen(p->dev) == ILO_GEN(6))
+ size *= 3;
+ break;
+ case PIPE_QUERY_TIMESTAMP:
+ case PIPE_QUERY_TIME_ELAPSED:
+ size = GEN6_PIPE_CONTROL__SIZE;
+ if (ilo_dev_gen(p->dev) == ILO_GEN(6))
+ size *= 2;
+ break;
+ case PIPE_QUERY_PIPELINE_STATISTICS:
+ if (ilo_dev_gen(p->dev) >= ILO_GEN(7)) {
+ const int num_regs = 10;
+ const int num_pads = 1;
+
+ size = GEN6_PIPE_CONTROL__SIZE +
+ GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
+ GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
+ } else {
+ const int num_regs = 8;
+ const int num_pads = 3;
+
+ size = GEN6_PIPE_CONTROL__SIZE * 3 +
+ GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
+ GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
+ }
+ break;
+ default:
+ size = 0;
+ break;
+ }
+
+ return size;
+}
+