i.MX PWM module's ipg_clk_s is for PWM register access, on most of i.MX
SoCs, this ipg_clk_s is from system ipg clock or perclk which is always
enabled, but on i.MX7D, the ipg_clk_s is from PWM1_CLK_ROOT which is
controlled by CCGR132, that means the CCGR132 MUST be enabled first
before accessing PWM registers on i.MX7D. This patch adds ipg clock
operation to make sure register access successfully on i.MX7D and it
fixes Linux kernel boot up hang during PWM driver probe.
Fixes:
4a23e6ee9f69 ("ARM: dts: imx7d-sdb: Restore pwm backlight support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
#define MX3_PWMPR_MAX 0xfffe
struct imx_chip {
#define MX3_PWMPR_MAX 0xfffe
struct imx_chip {
struct clk *clk_per;
void __iomem *mmio_base;
struct clk *clk_per;
void __iomem *mmio_base;
#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
+static int imx_pwm_clk_prepare_enable(struct pwm_chip *chip)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+ int ret;
+
+ ret = clk_prepare_enable(imx->clk_ipg);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(imx->clk_per);
+ if (ret) {
+ clk_disable_unprepare(imx->clk_ipg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void imx_pwm_clk_disable_unprepare(struct pwm_chip *chip)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+
+ clk_disable_unprepare(imx->clk_per);
+ clk_disable_unprepare(imx->clk_ipg);
+}
+
static void imx_pwm_get_state(struct pwm_chip *chip,
struct pwm_device *pwm, struct pwm_state *state)
{
static void imx_pwm_get_state(struct pwm_chip *chip,
struct pwm_device *pwm, struct pwm_state *state)
{
u32 period, prescaler, pwm_clk, ret, val;
u64 tmp;
u32 period, prescaler, pwm_clk, ret, val;
u64 tmp;
+ ret = imx_pwm_clk_prepare_enable(chip);
+ if (ret < 0)
+ return;
+
val = readl(imx->mmio_base + MX3_PWMCR);
if (val & MX3_PWMCR_EN) {
state->enabled = true;
val = readl(imx->mmio_base + MX3_PWMCR);
if (val & MX3_PWMCR_EN) {
state->enabled = true;
- ret = clk_prepare_enable(imx->clk_per);
+ ret = imx_pwm_clk_prepare_enable(chip);
if (ret)
return;
} else {
if (ret)
return;
} else {
} else {
state->duty_cycle = 0;
}
} else {
state->duty_cycle = 0;
}
+
+ imx_pwm_clk_disable_unprepare(chip);
}
static int imx_pwm_config_v1(struct pwm_chip *chip,
}
static int imx_pwm_config_v1(struct pwm_chip *chip,
- ret = clk_prepare_enable(imx->clk_per);
+ ret = imx_pwm_clk_prepare_enable(chip);
val &= ~MX1_PWMC_EN;
writel(val, imx->mmio_base + MX1_PWMC);
val &= ~MX1_PWMC_EN;
writel(val, imx->mmio_base + MX1_PWMC);
- clk_disable_unprepare(imx->clk_per);
+ imx_pwm_clk_disable_unprepare(chip);
}
static void imx_pwm_sw_reset(struct pwm_chip *chip)
}
static void imx_pwm_sw_reset(struct pwm_chip *chip)
if (cstate.enabled) {
imx_pwm_wait_fifo_slot(chip, pwm);
} else {
if (cstate.enabled) {
imx_pwm_wait_fifo_slot(chip, pwm);
} else {
- ret = clk_prepare_enable(imx->clk_per);
+ ret = imx_pwm_clk_prepare_enable(chip);
} else if (cstate.enabled) {
writel(0, imx->mmio_base + MX3_PWMCR);
} else if (cstate.enabled) {
writel(0, imx->mmio_base + MX3_PWMCR);
- clk_disable_unprepare(imx->clk_per);
+ imx_pwm_clk_disable_unprepare(chip);
if (imx == NULL)
return -ENOMEM;
if (imx == NULL)
return -ENOMEM;
+ imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+ if (IS_ERR(imx->clk_ipg)) {
+ dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
+ PTR_ERR(imx->clk_ipg));
+ return PTR_ERR(imx->clk_ipg);
+ }
+
imx->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(imx->clk_per)) {
dev_err(&pdev->dev, "getting per clock failed with %ld\n",
imx->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(imx->clk_per)) {
dev_err(&pdev->dev, "getting per clock failed with %ld\n",
if (imx == NULL)
return -ENODEV;
if (imx == NULL)
return -ENODEV;
+ imx_pwm_clk_disable_unprepare(&imx->chip);
+
return pwmchip_remove(&imx->chip);
}
return pwmchip_remove(&imx->chip);
}