abs x/y ok.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 18059c9..8ea09d8 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -138,8 +138,10 @@ entity alu is
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
             sp_pop_n        : in std_logic;
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
             sp_pop_n        : in std_logic;

-            abs_ea_n        : in std_logic;
-            zp_ea_n         : in std_logic;
+            abs_xy_n        : in std_logic;
+            abs_pg_next_n   : in std_logic;
+            zp_n            : in std_logic;
+            zp_xy_n         : in std_logic;

             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);


@@ -151,6 +153,7 @@ entity alu is
             abl             : out std_logic_vector (dsize - 1 downto 0);
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl_inc_carry   : out std_logic;
             abl             : out std_logic_vector (dsize - 1 downto 0);
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl_inc_carry   : out std_logic;

+            ea_carry        : out std_logic;

             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;
             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;


@@ -219,24 +222,32 @@ signal d1 : std_logic_vector (dsize - 1 downto 0);
 signal d2 : std_logic_vector (dsize - 1 downto 0);
 signal d_out : std_logic_vector (dsize - 1 downto 0);
 
 signal d2 : std_logic_vector (dsize - 1 downto 0);
 signal d_out : std_logic_vector (dsize - 1 downto 0);
 

-signal bal_reg : std_logic_vector (dsize - 1 downto 0);
-signal bah_reg : std_logic_vector (dsize - 1 downto 0);
+signal al_reg_in : std_logic_vector (dsize - 1 downto 0);
+signal ah_reg_in : std_logic_vector (dsize - 1 downto 0);
+signal al_reg : std_logic_vector (dsize - 1 downto 0);
+signal ah_reg : std_logic_vector (dsize - 1 downto 0);

 
 signal n : std_logic;
 signal z : std_logic;
 
 signal n : std_logic;
 signal z : std_logic;

+signal c_in : std_logic;

 signal c : std_logic;
 signal v : std_logic;
 signal c : std_logic;
 signal v : std_logic;

+
+signal al_buf_we : std_logic;
+signal ah_buf_we : std_logic;
+

 begin
 
 begin
 

-    bal_inst : d_flip_flop generic map (dsize) 
-            port map(clk, '1', '1', '0', bal, bal_reg);
-    bah_inst : d_flip_flop generic map (dsize) 
-            port map(clk, '1', '1', '0', bah, bah_reg);
+    al_buf : d_flip_flop generic map (dsize) 
+            port map(clk, '1', '1', al_buf_we, al_reg_in, al_reg);
+    ah_buf : d_flip_flop generic map (dsize) 
+            port map(clk, '1', '1', ah_buf_we, ah_reg_in, ah_reg);

 
     alu_inst : alu_core generic map (dsize)
 
     alu_inst : alu_core generic map (dsize)

-            port map (sel, d1, d2, d_out, carry_in, n, z, c, v);
+            port map (sel, d1, d2, d_out, c_in, n, z, c, v);

 
 

-    alu_p : process (clk, pcl_inc_n, pch_inc_n, abs_ea_n, zp_ea_n, arith_en_n, 
+    alu_p : process (clk, pcl_inc_n, pch_inc_n, sph_oe_n, sp_push_n, sp_pop_n,
+                    abs_xy_n, abs_pg_next_n, zp_n, zp_xy_n, arith_en_n,

                     instruction, 
                     int_d_bus, acc_out, index_bus, bal, bal, carry_in, d_out, 
                     n, z, c, v)
                     instruction, 
                     int_d_bus, acc_out, index_bus, bal, bal, carry_in, d_out, 
                     n, z, c, v)


@@ -248,10 +259,12 @@ begin
         pcl_inc_carry <= c;
 
         --keep the value in the cycle
         pcl_inc_carry <= c;
 
         --keep the value in the cycle

+        al_buf_we <= '0';
+        al_reg_in <= bal;

         if (clk = '0') then
             abl <= bal;
         else
         if (clk = '0') then
             abl <= bal;
         else

-            abl <= bal_reg;
+            abl <= al_reg;

         end if;
         abh <= bah;
 
         end if;
         abh <= bah;
 


@@ -277,10 +290,12 @@ begin
             d1 <= bal;
             alu_res <= d_out;
 
             d1 <= bal;
             alu_res <= d_out;
 

+            al_buf_we <= '0';
+            al_reg_in <= bal;

             if (clk = '0') then
                 abl <= bal;
             else
             if (clk = '0') then
                 abl <= bal;
             else

-                abl <= bal_reg;
+                abl <= al_reg;

             end if;
         else
             ---case push
             end if;
         else
             ---case push


@@ -291,9 +306,33 @@ begin
             if (clk = '0') then
                 abl <= bal;
             else
             if (clk = '0') then
                 abl <= bal;
             else

-                abl <= bal_reg;
+                abl <= al_reg;

             end if;
         end if;
             end if;
         end if;

+    elsif (abs_xy_n = '0') then
+        if (abs_pg_next_n = '0') then
+            sel <= ALU_INC;
+            d1 <= bah;
+            ea_carry <= '0';
+
+            al_buf_we <= '1';
+            abh <= d_out;
+            ---al is in the al_reg.
+            abl <= al_reg;
+        else
+            sel <= ALU_ADC;
+            d1 <= bal;
+            d2 <= index_bus;
+            c_in <= '0';
+            ea_carry <= c;
+
+            ---keep al for page crossed case
+            al_buf_we <= '0';
+            al_reg_in <= d_out;
+            abh <= bah;
+            abl <= d_out;
+        end if;
+

     elsif (arith_en_n = '0') then
             --instruction is aaabbbcc format.
             if instruction (1 downto 0) = "01" then
     elsif (arith_en_n = '0') then
             --instruction is aaabbbcc format.
             if instruction (1 downto 0) = "01" then

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 1b307ae..1f7ff19 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -34,6 +34,11 @@ entity decoder is
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);

+            abs_xy_n        : out std_logic;
+            ea_carry        : in  std_logic;
+            abs_pg_next_n   : out std_logic;
+            zp_n            : out std_logic;
+            zp_xy_n         : out std_logic;

             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
             stat_set_flg_n  : out std_logic;
             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
             stat_set_flg_n  : out std_logic;


@@ -189,6 +194,11 @@ begin
     x_cmd <= "1111";
     y_cmd <= "1111";
 
     x_cmd <= "1111";
     y_cmd <= "1111";
 

+    abs_xy_n <= '1';
+    abs_pg_next_n <= '1';
+    zp_n <= '1';
+    zp_xy_n <= '1';
+

     stat_dec_oe_n <= '1';
     stat_bus_oe_n <= '1';
     stat_set_flg_n <= '1';
     stat_dec_oe_n <= '1';
     stat_bus_oe_n <= '1';
     stat_set_flg_n <= '1';


@@ -309,6 +319,10 @@ end  procedure;
 procedure ea_x_out is
 begin
     -----calucurate and output effective addr
 procedure ea_x_out is
 begin
     -----calucurate and output effective addr

+    back_oe(x_cmd, '0');
+    dl_al_oe_n <= '0';
+    dl_ah_oe_n <= '0';
+    abs_xy_n <= '0';

 end  procedure;
 
 --A.2. internal execution on memory data
 end  procedure;
 
 --A.2. internal execution on memory data


@@ -318,6 +332,35 @@ end  procedure;
 
 procedure a2_absx is
 begin
 
 procedure a2_absx is
 begin

+    if exec_cycle = T1 then
+        fetch_low;
+    elsif exec_cycle = T2 then
+        abs_fetch_high;
+    elsif exec_cycle = T3 then
+        --ea calc & lda
+        abs_latch_out;
+        ea_x_out;
+        dbuf_int_oe_n <= '0';
+        --instruction specific operation wriiten in the caller position.
+        next_cycle <= T4;
+    elsif exec_cycle = T4 then
+        if ea_carry = '1' then
+            --case page boundary crossed.
+            d_print("absx 5 (page boudary crossed.)");
+            abs_latch_out;
+            ea_x_out;
+            dbuf_int_oe_n <= '0';
+            --next page.
+            abs_pg_next_n <= '0';
+            --redo inst.
+            next_cycle <= T0;
+        else
+            --case page boundary not crossed. do the fetch op.
+            d_print("absx 5 (fetch)");
+            fetch_inst;
+            next_cycle <= T1;
+        end if;
+    end if;

 end  procedure;
 
 
 end  procedure;
 
 


@@ -692,8 +735,14 @@ end  procedure;
                     a2_absx;
                     if exec_cycle = T3 then
                         --lda.
                     a2_absx;
                     if exec_cycle = T3 then
                         --lda.

+                        front_we(acc_cmd, '0');

                         set_nz_from_bus;
                     elsif exec_cycle = T4 then
                         set_nz_from_bus;
                     elsif exec_cycle = T4 then

+                        if ea_carry = '1' then
+                            --redo lda
+                            front_we(acc_cmd, '0');
+                            set_nz_from_bus;
+                        end if;

                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then
                     end if;
 
                 elsif instruction  = conv_std_logic_vector(16#b9#, dsize) then


@@ -1273,6 +1322,11 @@ end  procedure;
                 x_cmd <= "1111";
                 y_cmd <= "1111";
 
                 x_cmd <= "1111";
                 y_cmd <= "1111";
 

+                abs_xy_n <= '1';
+                abs_pg_next_n <= '1';
+                zp_n <= '1';
+                zp_xy_n <= '1';
+

                 stat_dec_oe_n <= '1';
                 stat_bus_oe_n <= '1';
                 stat_set_flg_n <= '1';
                 stat_dec_oe_n <= '1';
                 stat_bus_oe_n <= '1';
                 stat_set_flg_n <= '1';

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index de6c607..a86133b 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -55,6 +55,11 @@ component decoder
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);

+            abs_xy_n        : out std_logic;
+            ea_carry        : in  std_logic;
+            abs_pg_next_n   : out std_logic;
+            zp_n            : out std_logic;
+            zp_xy_n         : out std_logic;

             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
             stat_set_flg_n  : out std_logic;
             stat_dec_oe_n   : out std_logic;
             stat_bus_oe_n   : out std_logic;
             stat_set_flg_n  : out std_logic;


@@ -77,8 +82,10 @@ component alu
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
             sp_pop_n        : in std_logic;
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
             sp_pop_n        : in std_logic;

-            abs_ea_n        : in std_logic;
-            zp_ea_n         : in std_logic;
+            abs_xy_n        : in std_logic;
+            abs_pg_next_n   : in std_logic;
+            zp_n            : in std_logic;
+            zp_xy_n         : in std_logic;

             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
             arith_en_n      : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);


@@ -90,6 +97,7 @@ component alu
             abl             : out std_logic_vector (dsize - 1 downto 0);
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl_inc_carry   : out std_logic;
             abl             : out std_logic_vector (dsize - 1 downto 0);
             abh             : out std_logic_vector (dsize - 1 downto 0);
             pcl_inc_carry   : out std_logic;

+            ea_carry        : out std_logic;

             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;
             carry_in        : in std_logic;
             negative        : out std_logic;
             zero            : out std_logic;


@@ -218,8 +226,11 @@ end component;
     signal pcl_inc_n : std_logic;
     signal pch_inc_n : std_logic;
     signal pcl_inc_carry : std_logic_vector(0 downto 0);
     signal pcl_inc_n : std_logic;
     signal pch_inc_n : std_logic;
     signal pcl_inc_carry : std_logic_vector(0 downto 0);

-    signal abs_ea_n : std_logic;
-    signal zp_ea_n : std_logic;
+    signal abs_xy_n        : std_logic;
+    signal ea_carry        : std_logic;
+    signal abs_pg_next_n   : std_logic;
+    signal zp_n            : std_logic;
+    signal zp_xy_n         : std_logic;

     signal arith_en_n : std_logic;
                     
     signal alu_n : std_logic;
     signal arith_en_n : std_logic;
                     
     signal alu_n : std_logic;


@@ -334,6 +345,11 @@ begin
                     acc_cmd,
                     x_cmd,
                     y_cmd,
                     acc_cmd,
                     x_cmd,
                     y_cmd,

+                    abs_xy_n,
+                    ea_carry,
+                    abs_pg_next_n,
+                    zp_n,
+                    zp_xy_n,

                     stat_dec_oe_n, 
                     stat_bus_oe_n, 
                     stat_set_flg_n, 
                     stat_dec_oe_n, 
                     stat_bus_oe_n, 
                     stat_set_flg_n, 


@@ -352,8 +368,10 @@ begin
                     sph_oe_n,
                     sp_push_n,
                     sp_pop_n,
                     sph_oe_n,
                     sp_push_n,
                     sp_pop_n,

-                    abs_ea_n,
-                    zp_ea_n,
+                    abs_xy_n,
+                    abs_pg_next_n,
+                    zp_n,
+                    zp_xy_n,

                     arith_en_n,
                     instruction,
                     d_bus,
                     arith_en_n,
                     instruction,
                     d_bus,


@@ -365,6 +383,7 @@ begin
                     abl,
                     abh,
                     pcl_inc_carry(0),
                     abl,
                     abh,
                     pcl_inc_carry(0),

+                    ea_carry,

                     alu_c_in,
                     alu_n,
                     alu_z,
                     alu_c_in,
                     alu_n,
                     alu_z,