Change-Id: I6de36584f084f75f828eedece1d7c7abcc0648ef

diff --git a/VGADisplay/src/FIFO.v b/VGADisplay/src/FIFO.v
new file mode 100644 (file)
index 0000000..24c6cbf
--- /dev/null
+++ b/VGADisplay/src/FIFO.v
@@ -0,0 +1,47 @@
+module FIFO (\r
+       p_reset, m_clock, i_we1,\r
+       i_wadrs1, i_wdata1, i_we2,\r
+       i_wadrs2, i_wdata2, i_radrs1,\r
+       o_rdasrs1, i_radrs2, o_rdasrs2,\r
+       i_clock\r
+);\r
+\r
+       input p_reset ;\r
+       input m_clock ;\r
+       \r
+       input i_we1 ;\r
+       input [6:0] i_wadrs1 ;\r
+       input [7:0] i_wdata1 ;\r
+\r
+       input i_clock ;\r
+       input i_we2 ;\r
+       input [6:0] i_wadrs2 ;\r
+       input [7:0] i_wdata2 ;\r
+       \r
+       input  [6:0] i_radrs1 ;\r
+       output [7:0] o_rdasrs1 ;\r
+\r
+       input  [6:0] i_radrs2 ;\r
+       output [7:0] o_rdasrs2 ;\r
+\r
+       reg [6:0] r_rdadrs1 ;\r
+       reg [6:0] r_rdadrs2 ;\r
+       \r
+       (* remstyle = "no_rw_check" *) reg [7:0] mem1[127:0] ;\r
+       (* remstyle = "no_rw_check" *) reg [7:0] mem2[127:0] ;\r
+       \r
+       // memory write command\r
+       always @ (posedge m_clock) begin\r
+               if(we1) mem1[i_wadrs1] <= i_wdata1 ;\r
+               if(we2) mem1[i_wadrs2] <= i_wdata2 ;\r
+       end\r
+\r
+       always @ (posedge i_clock) begin\r
+               r_rdadrs1 <= i_radrs1 ;\r
+               r_rdadrs2 <= i_radrs2 ;\r
+       end\r
+\r
+       assign q = mem1[r_rdadrs1] ;\r
+       assign q = mem2[r_rdadrs2] ;\r
+       \r
+endmodule
\ No newline at end of file