- --instruction is aaabbbcc format.
- if instruction (1 downto 0) = "01" then
- if instruction (7 downto 5) = "000" then
- d_print("ora");
- elsif instruction (7 downto 5) = "001" then
- d_print("and");
- elsif instruction (7 downto 5) = "010" then
- d_print("eor");
- elsif instruction (7 downto 5) = "011" then
- d_print("adc");
- elsif instruction (7 downto 5) = "110" then
- d_print("cmp");
- --cmpare A - M.
- sel <= ALU_CMP;
- d1 <= acc_out;
- d2 <= int_d_bus;
- alu_res <= d_out;
-
- elsif instruction (7 downto 5) = "111" then
- d_print("sbc");
- end if;
- elsif instruction (1 downto 0) = "10" then
- if instruction (7 downto 5) = "000" then
- d_print("asl");
- elsif instruction (7 downto 5) = "001" then
- d_print("rol");
- elsif instruction (7 downto 5) = "010" then
- d_print("lsr");
- elsif instruction (7 downto 5) = "011" then
- d_print("ror");
- elsif instruction (7 downto 5) = "110" then
- d_print("dec");
- elsif instruction (7 downto 5) = "111" then
- d_print("inc");
- end if;
- elsif instruction (1 downto 0) = "00" then
- if instruction (7 downto 5) = "001" then
- d_print("bit");
- elsif instruction (7 downto 5) = "110" then
- d_print("cpy");
- elsif instruction (7 downto 5) = "111" then
- d_print("cpx");
- end if; --if instruction (7 downto 5) = "001" then
- end if; --if instruction (1 downto 0) = "01"
+
+ arith_buf_we <= '0';
+ abl <= (others => 'Z');
+ abh <= (others => 'Z');
+
+ if instruction = conv_std_logic_vector(16#ca#, dsize) then
+ d_print("dex");
+
+ elsif instruction = conv_std_logic_vector(16#88#, dsize) then
+ --d_print("dey");
+ sel <= ALU_DEC;
+ d1 <= index_bus;
+ c_in <= '0';
+
+ negative <= n;
+ zero <= z;
+ output_d_bus;
+
+ elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
+ --d_print("inx");
+ sel <= ALU_INC;
+ d1 <= index_bus;
+ c_in <= '0';
+
+ negative <= n;
+ zero <= z;
+ output_d_bus;
+
+ elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
+ d_print("iny");
+
+ --instruction is aaabbbcc format.
+ elsif instruction (1 downto 0) = "01" then
+ if instruction (7 downto 5) = "000" then
+ d_print("ora");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("and");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("eor");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("adc");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cmp");
+ --cmpare A - M.
+ sel <= ALU_CMP;
+ d1 <= acc_out;
+ d2 <= int_d_bus;
+ alu_res <= d_out;
+
+ elsif instruction (7 downto 5) = "111" then
+ d_print("sbc");
+ end if;
+ elsif instruction (1 downto 0) = "10" then
+ if instruction (7 downto 5) = "000" then
+ d_print("asl");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("rol");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("lsr");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("ror");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("dec");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("inc");
+ end if;
+ elsif instruction (1 downto 0) = "00" then
+ if instruction (7 downto 5) = "001" then
+ d_print("bit");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cpy");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("cpx");
+ end if; --if instruction (7 downto 5) = "001" then
+ end if; --if instruction = conv_std_logic_vector(16#ca#, dsize)