sim: bfin: fix UART LSR read-only bit saturation

A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 3470143..6785044 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2011-05-09  Mike Frysinger  <vapier@gentoo.org>
+
+       * dv-bfin_uart2.c (bfin_uart_io_read_buffer): Clear DR/THRE/TEMT bits
+       from uart->lsr before setting them.
+
 2011-04-27  Mike Frysinger  <vapier@gentoo.org>
 
        * dv-bfin_dmac.c (bfin_dmac): Constify pmap array.

diff --git a/sim/bfin/dv-bfin_uart2.c b/sim/bfin/dv-bfin_uart2.c
index facde1c..179574d 100644 (file)
--- a/sim/bfin/dv-bfin_uart2.c
+++ b/sim/bfin/dv-bfin_uart2.c
@@ -151,6 +151,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
       bfin_uart_reschedule (me);
       break;
     case mmr_offset(lsr):
+      uart->lsr &= ~(DR | THRE | TEMT);
       uart->lsr |= bfin_uart_get_status (me);
     case mmr_offset(thr):
     case mmr_offset(msr):