drm/amd/display: Fix applying surface to underlay pipe

1. Locking all pipes before doing any changes
2. Applying surface for both top and bottom pipes

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6409d4d..c0889ad 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1331,32 +1331,41 @@ void dc_update_surfaces_and_stream(struct dc *dc,
        if (!surface_count)  /* reset */
                core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
 
+       /* Lock pipes for provided surfaces */
        for (i = 0; i < surface_count; i++) {
                struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
 
                for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-                       struct pipe_ctx *cur_pipe_ctx;
-                       bool is_new_pipe_surface = true;
 
                        if (pipe_ctx->surface != surface)
                                continue;
-
-                       if (update_type >= UPDATE_TYPE_MED) {
-                               /* only apply for top pipe */
-                               if (!pipe_ctx->top_pipe) {
-                                       core_dc->hwss.apply_ctx_for_surface(core_dc,
-                                                        surface, context);
-                                       context_timing_trace(dc, &context->res_ctx);
-                               }
-                       }
-
                        if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
                                core_dc->hwss.pipe_control_lock(
                                                core_dc,
                                                pipe_ctx,
                                                true);
                        }
+               }
+       }
+
+       /* Perform requested Updates */
+       for (i = 0; i < surface_count; i++) {
+               struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
+
+               if (update_type >= UPDATE_TYPE_MED) {
+                               core_dc->hwss.apply_ctx_for_surface(
+                                               core_dc, surface, context);
+                               context_timing_trace(dc, &context->res_ctx);
+               }
+
+               for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
+                       struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+                       struct pipe_ctx *cur_pipe_ctx;
+                       bool is_new_pipe_surface = true;
+
+                       if (pipe_ctx->surface != surface)
+                               continue;
 
                        if (srf_updates[i].flip_addr)
                                core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
@@ -1387,6 +1396,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
                }
        }
 
+       /* Unlock pipes */
        for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];