drm/amdgpu: fix no interrupt issue for renoir emu

In renoir's ih model, there's a change in mmIH_CHICKEN
register, that limits IH to use physical address directly.
Those chicken bits need to be programmed first.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index c1c0a39..4fac1e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -247,7 +247,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
        }
 
-       if (adev->asic_type == CHIP_ARCTURUS &&
+       if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) &&
                adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
                if (adev->irq.ih.use_bus_addr) {
                        ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);