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drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 31 Mar 2021 10:57:25 +0000 (13:57 +0300)
committerRob Clark <robdclark@chromium.org>
Wed, 7 Apr 2021 18:05:46 +0000 (11:05 -0700)
These drivers do not use vco_delay variable, so drop it from all of
them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-15-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

index d81cea6..91ae0f8 100644 (file)
@@ -99,7 +99,6 @@ struct dsi_pll_10nm {
        /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
        spinlock_t postdiv_lock;
 
-       int vco_delay;
        struct dsi_pll_config pll_configuration;
        struct dsi_pll_regs reg_setup;
 
@@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
        pll = &pll_10nm->base;
        pll->cfg = phy->cfg;
 
-       pll_10nm->vco_delay = 1;
-
        ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
        if (ret) {
                DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
index 7fe7c83..434d02f 100644 (file)
@@ -122,8 +122,6 @@ struct dsi_pll_14nm {
        void __iomem *phy_cmn_mmio;
        void __iomem *mmio;
 
-       int vco_delay;
-
        struct dsi_pll_input in;
        struct dsi_pll_output out;
 
@@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
        pll = &pll_14nm->base;
        pll->cfg = phy->cfg;
 
-       pll_14nm->vco_delay = 1;
-
        ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
        if (ret) {
                DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
index d725ceb..321d23b 100644 (file)
@@ -99,7 +99,6 @@ struct dsi_pll_7nm {
        /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
        spinlock_t postdiv_lock;
 
-       int vco_delay;
        struct dsi_pll_config pll_configuration;
        struct dsi_pll_regs reg_setup;
 
@@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
        pll = &pll_7nm->base;
        pll->cfg = phy->cfg;
 
-       pll_7nm->vco_delay = 1;
-
        ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
        if (ret) {
                DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);