MachineInstrBuilder MIB(MF, NewMI);
bool isPatchPoint = MI->getOpcode() == TargetOpcode::PATCHPOINT;
+ // For PatchPoint, the call args are not foldable.
+ unsigned NumCallArgs = MI->getOperand(StartIdx+3).getImm();
StartIdx = isPatchPoint ?
- StartIdx + MI->getOperand(StartIdx+3).getImm() + 5 :
+ StartIdx + NumCallArgs + 5 :
StartIdx + 2;
+ // Return false if any operands requested for folding are not foldable (not
+ // part of the stackmap's live values).
+ for (SmallVectorImpl<unsigned>::const_iterator I = Ops.begin(), E = Ops.end();
+ I != E; ++I) {
+ if (*I < StartIdx)
+ return 0;
+ }
// No need to fold return, the meta data, and function arguments
for (unsigned i = 0; i < StartIdx; ++i)
MIB.addOperand(MI->getOperand(i));
; Num Constants
; CHECK-NEXT: .long 0
; Num Callsites
-; CHECK-NEXT: .long 6
+; CHECK-NEXT: .long 7
; test
; CHECK-NEXT: .long 0
-; CHECK-NEXT: .long L{{.*}}-_test
+; CHECK-LABEL: .long L{{.*}}-_test
; CHECK-NEXT: .short 0
; 3 locations
; CHECK-NEXT: .short 3
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-NEXT: .long 1
-; CHECK-NEXT: .long L{{.*}}-_property_access1
+; CHECK-LABEL: .long L{{.*}}-_property_access1
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-NEXT: .long 2
-; CHECK-NEXT: .long L{{.*}}-_property_access2
+; CHECK-LABEL: .long L{{.*}}-_property_access2
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; property access 3 - %obj is a frame index
; CHECK-NEXT: .long 3
-; CHECK-NEXT: .long L{{.*}}-_property_access3
+; CHECK-LABEL: .long L{{.*}}-_property_access3
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; anyreg_test1
; CHECK-NEXT: .long 4
-; CHECK-NEXT: .long L{{.*}}-_anyreg_test1
+; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
; anyreg_test2
; CHECK-NEXT: .long 5
-; CHECK-NEXT: .long L{{.*}}-_anyreg_test2
+; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
ret i64 %ret
}
+; Test spilling the return value of an anyregcc call.
+;
+; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
+;
+; CHECK-LABEL: .long 12
+; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 3
+; Loc 0: Register (some register that will be spilled to the stack)
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .long 0
+; Loc 1: Register RDI
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 5
+; CHECK-NEXT: .long 0
+; Loc 1: Register RSI
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
+; CHECK-NEXT: .long 0
+define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
+entry:
+ %result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+ tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
+ ret i64 %result
+}
+
declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)
-