/**
-* VGA\81@Signal Generate Circuit
+* Video Graphic Array\81@Signal Generate Circuit
* Module name is "vga_generate"
* @auther Yujiro Kaneko
* @version 1.2
#define VCNT_1SEC 26'd25000000
declare vga_gen interface {
- input i_clk50M ; // 50MHz main clock
+ input i_clk50 ; // 50MHz main clock
+ input i_fifo_fst ; // FIFO rst
input m_clock ;
input p_reset ;
- output o_vsync ;
- output o_hsync ;
- output o_vga_r[4] ;
- output o_vga_g[4] ;
- output o_vga_b[4] ;
-
- input i_wrdata1[8] ;
- input i_wrdata2[8] ;
- input i_wradrs1[8] ;
- input i_wradrs2[8] ;
-
- func_in fi_fifo1_write( i_wradrs1, i_wrdata1 ) ;
- func_in fi_fifo2_write( i_wradrs2, i_wrdata2 ) ;
-
- output outled ;
- output o_vcnt[10] ;
+ output o_vsync ; // Vertical Sync
+ output o_hsync ; // Horizontal Hync
+ output o_vga_r[4] ; // VGA RED
+ output o_vga_g[4] ; // VGA GREEN
+ output o_vga_b[4] ; // VGA BLUE
+ output o_dummy_rgb[3] ; // VGA dummy signal
+ output o_vcnt[10] ; // V sync Count
+
+ /* FIFO write terminal */
+ input i_wrdata[8] ;
+ func_in fi_fifo_write( i_wrdata ) ;
+
+ /* FIFO terminal */
+ output o_rdack ;
+
+ output o_led ;
}
module vga_gen {
- func_self fs_fifo1_read() ;
- func_self fs_fifo2_read() ;
-
- func_self fs_fifo1_exec() ;
- func_self fs_fifo2_exec() ;
+ func_self fs_fifo_read() ; // FIFO read terminal
+ wire w_rddata[8] ; // FIFO read wire
+ func_self fs_fifo_ack(w_rddata) ;
+ func_self fs_initialize() ;
- func_self fs_fifo1_reset() ;
- func_self fs_fifo2_reset() ;
-
- reg r_bit_number[5] = 0 ;
+ reg r_data1[8] = 0 ;
+ reg r_data2[8] = 0 ;
+ reg r_reg_cnt = 0 ;
+ reg r_bit_cnt[3] = 0 ;
reg r_vsync = 0 ;
reg r_hsync = 0 ;
reg r_vcnt[10] = 0 ;
reg r_hcnt[10] = 0 ;
- reg cnt[26] = 0 ;
- reg testled = 0 ;
+ reg r_cnt[26] = 0 ;
reg r_outcnt[3] = 0 ;
reg r_outclr[7] = 0 ;
reg r_vcnt_hld = 0 ;
- wire w_rddata1[24] ;
- wire w_rddata2[24] ;
-
- reg r_rdadrs1[8] = 0 ;
- reg r_rdadrs2[8] = 0 ;
-
+ reg r_led = 0 ;
+ reg r_init_flg = 0 ;
+ reg r_trg[3] = 0 ;
+
vga_ram u_FIFO ;
{
- /* FIFO assign */
- u_FIFO.i_clk50 = i_clk50M ;
- u_FIFO.i_clk100 = m_clock ;
-
- u_FIFO.i_we1 = fi_fifo1_write ;
- u_FIFO.i_we2 = fi_fifo2_write ;
- u_FIFO.i_wrdata1 = i_wrdata1 ;
- u_FIFO.i_wrdata2 = i_wrdata2 ;
- u_FIFO.i_wradrs1 = i_wradrs1 ;
- u_FIFO.i_wradrs2 = i_wradrs2 ;
- u_FIFO.i_re1 = fs_fifo1_read ;
- u_FIFO.i_re2 = fs_fifo2_read ;
- w_rddata1 = u_FIFO.o_rddata1 ;
- w_rddata2 = u_FIFO.o_rddata2 ;
- u_FIFO.i_rdadrs1 = r_rdadrs1 ;
- u_FIFO.i_rdadrs2 = r_rdadrs2 ;
- o_vcnt = r_vcnt ;
-
- r_vcnt_hld := r_vcnt[0] ;
-
- /* LED test */
- outled = testled ;
+ r_trg := { r_trg[1:0], 0b1 } ;
+ if(r_trg == 0b011) fs_initialize() ;
+
+ /* VGA Generate Node */
o_vsync = r_vsync ;
o_hsync = r_hsync ;
+ /* FIFO assign */
+ u_FIFO.i_clk50 = i_clk50 ;
+ u_FIFO.i_clk25 = m_clock ;
+ o_rdack = u_FIFO.o_rdack ;
+ u_FIFO.i_we = fi_fifo_write ;
+ u_FIFO.i_wrdata = i_wrdata ;
+ u_FIFO.i_rst = i_fifo_fst ;
+ u_FIFO.i_re = fs_fifo_read ;
+
+ /* TEST LED cnt routine */
+ o_led = r_led ;
+
any {
- ~r_vcnt_hld & r_vcnt[0] : {
- fs_fifo1_reset() ;
- }
- r_vcnt_hld & ~r_vcnt[0] : {
- fs_fifo2_reset() ;
- }
- }
-
- /* test led count routine */
- any {
- cnt == VCNT_1SEC : {
- cnt := 0 ;
- testled := ~testled ;
+ r_cnt == VCNT_1SEC : {
+ r_cnt := 0 ;
+ r_led := ~r_led ;
}
else : {
- cnt++ ;
+ r_cnt++ ;
}
}
- /* vsync hsync generate routine */
- if( r_hcnt < H_BACKP_MAX ) {
- r_hcnt++ ;
- } else {
- r_hcnt := 0 ;
- if( r_vcnt < V_BACKP_MAX ) {
- r_vcnt++ ;
+ /* VSync & HSync\81@\90¶\90¬\83\8b\81[\83`\83\93 */
+ if(r_init_flg) {
+ if( r_hcnt < H_BACKP_MAX ) {
+ r_hcnt++ ;
} else {
- r_vcnt := 0 ;
+ r_hcnt := 0 ;
+ if( r_vcnt < V_BACKP_MAX ) {
+ r_vcnt++ ;
+ } else {
+ r_vcnt := 0 ;
+ }
}
}
- // HACTMAX640 VACTMAX480
+
+ // HACTMAX640 VACTMAX480 \83J\83\89\81[\95`\89æ\83G\83\8a\83A
if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
- any {
- ~r_vcnt[0] : fs_fifo1_exec() ;
- r_vcnt[0] : fs_fifo2_exec() ;
- }
-
- any {
- r_bit_number == 5'd23 : {
- r_bit_number := 0 ;
+ // \83f\81[\83^\83o\83b\83t\83@\89^\97p\83J\83E\83\93\83^\81i\83e\83X\83g\97p\81j
+ if( r_init_flg ) {
+ r_bit_cnt++ ; // \83r\83b\83g\83J\83E\83\93\83g\83A\83b\83v
+
+ // \83\8c\83W\83X\83^\83J\83E\83\93\83g\94½\93]
+ if(r_bit_cnt==0b111) {
+ r_reg_cnt := ~r_reg_cnt ;
+ fs_fifo_read() ;
+ }
+
+ // FIFO\93Ç\82Ý\8fo\82µ\92l\83o\83b\83t\83@\83\8a\83\93\83O
+ if( fs_fifo_ack ) {
any {
- ~r_vcnt[0] : fs_fifo1_read() ;
- r_vcnt[0] : fs_fifo2_read() ;
+ ~r_reg_cnt : r_data2 := w_rddata ;
+ r_reg_cnt : r_data1 := w_rddata ;
}
}
- else : {
- r_bit_number++ ;
+
+ any {
+ r_reg_cnt == 0b0 : o_dummy_rgb = 3#(r_data1[r_reg_cnt]) ;
+ // (r_reg_cnt == 0b1)
+ else : o_dummy_rgb = 3#(r_data2[r_reg_cnt]) ;
}
}
-
+
+
/* \83J\83\89\81[\83o\81[\8dì\90¬ */
-/*
if( r_outcnt < 3'd4 ) {
r_outcnt++ ;
} else {
if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ;
else o_vga_b = 0 ;
-
if( ~r_outclr[5]) o_vga_r = ~r_outclr[3:0] ;
else o_vga_r = 0 ;
-
if( ~r_outclr[6]) o_vga_g = ~r_outclr[3:0] ;
else o_vga_g = 0 ;
-*/
+
} else {
+ // \83J\83\89\81[\95`\89æ\82µ\82È\82¢\83G\83\8a\83A
any {
r_hcnt == H_ACT_MAX : {
- /* VGA\81@null\81@ */
o_vga_r = 0 ;
o_vga_g = 0 ;
o_vga_b = 0 ;
r_outcnt := 0 ;
r_outclr := 0 ;
- r_bit_number := 0 ;
}
r_hcnt == H_FRONTP_MAX : {
r_hsync := 0 ;
}
any {
- r_vcnt == V_ACT_MAX : {
- ;
- }
- r_vcnt == V_FRONTP_MAX : {
- r_vsync := 0 ;
- }
- r_vcnt == V_SYNC_MAX : {
- r_vsync := 1 ;
- }
+ r_vcnt == V_ACT_MAX : ;
+ r_vcnt == V_FRONTP_MAX : r_vsync := 0 ;
+ r_vcnt == V_SYNC_MAX : r_vsync := 1 ;
}
}
- func fs_fifo1_exec {
- if(w_rddata1[r_bit_number]){
- o_vga_r = 4'b1111 ;
- o_vga_g = 4'b1111 ;
- o_vga_b = 4'b1111 ;
- } else {
- o_vga_r = 4'b0000 ;
- o_vga_g = 4'b0000 ;
- o_vga_b = 4'b0000 ;
- }
+ // VGA Gen initialize command
+ func fs_initialize seq {
+ // \83f\81[\83^\83o\83b\83t\83@\82P\81C\82Q\82ÉFIFO\82Ì\92l\82ð\8ai\94[
+ fs_fifo_read() ;
+ r_data1 := u_FIFO.o_rddata ;
+ fs_fifo_read() ;
+ r_data2 := u_FIFO.o_rddata ;
+ r_init_flg := 1 ;
}
- func fs_fifo2_exec {
- if(w_rddata2[r_bit_number]){
- o_vga_r = 4'b1111 ;
- o_vga_g = 4'b1111 ;
- o_vga_b = 4'b1111 ;
- } else {
- o_vga_r = 4'b0000 ;
- o_vga_g = 4'b0000 ;
- o_vga_b = 4'b0000 ;
-
- }
- }
-
- func fs_fifo1_read {
- r_rdadrs1 := r_rdadrs1 + 8'd3 ;
- }
-
- func fs_fifo2_read {
- r_rdadrs2 := r_rdadrs2 + 8'd3 ;
+ // FIFO read command
+ func fs_fifo_read seq {
+ ;
+ fs_fifo_ack( u_FIFO.o_rddata ) ;
}
-
- func fs_fifo1_reset {
- r_rdadrs1 := 8'd0 ;
- }
-
- func fs_fifo2_reset {
- r_rdadrs2 := 8'd0 ;
- }
-} //module end
\ No newline at end of file
+}
+//module end
\ No newline at end of file
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