void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
}
}
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
-{
- return mmu_idx & MMU_2STAGE_BIT;
-}
-
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
{
CPURISCVState *env = &cpu->env;
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
}
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
g_assert_not_reached();
}
env->badaddr = addr;
- env->two_stage_lookup = env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx);
+ env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
env->two_stage_indirect_lookup = false;
cpu_loop_exit_restore(cs, retaddr);
}
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
- if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
pmu_tlb_fill_incr_ctr(cpu, access_type);
if (env->virt_enabled ||
- ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+ ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
} else {
raise_mmu_exception(env, address, access_type, pmp_violation,
first_stage_error,
- env->virt_enabled ||
- riscv_cpu_two_stage_lookup(mmu_idx),
+ env->virt_enabled || mmuidx_2stage(mmu_idx),
two_stage_indirect_error);
cpu_loop_exit_restore(cs, retaddr);
}