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drm/amdgpu: add ih ip block for navy_flounder
authorJiansong Chen <Jiansong.Chen@amd.com>
Wed, 12 Feb 2020 14:32:01 +0000 (22:32 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 15 Jul 2020 16:46:19 +0000 (12:46 -0400)
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/nv.c

index 471dc82..fdabaf0 100644 (file)
@@ -270,6 +270,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
                if (ih->use_bus_addr) {
                        switch (adev->asic_type) {
                        case CHIP_SIENNA_CICHLID:
+                       case CHIP_NAVY_FLOUNDER:
                                ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
                                ih_chicken = REG_SET_FIELD(ih_chicken,
                                                IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
index 07f9d61..d7688b9 100644 (file)
@@ -526,6 +526,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
        case CHIP_NAVY_FLOUNDER:
                amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
                amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
                break;
        default:
                return -EINVAL;