coresight: etm4x: Cleanup TRCIDR5 register accesses

This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-6-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index c52ab7f..3f42631 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1188,26 +1188,20 @@ static void etm4_init_arch_data(void *info)
 
        etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
        /* NUMEXTIN, bits[8:0] number of external inputs implemented */
-       drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
+       drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
        /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
-       drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
+       drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
        /* ATBTRIG, bit[22] implementation can support ATB triggers? */
-       if (BMVAL(etmidr5, 22, 22))
-               drvdata->atbtrig = true;
-       else
-               drvdata->atbtrig = false;
+       drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
        /*
         * LPOVERRIDE, bit[23] implementation supports
         * low-power state override
         */
-       if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
-               drvdata->lpoverride = true;
-       else
-               drvdata->lpoverride = false;
+       drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
        /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
-       drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
+       drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
        /* NUMCNTR, bits[30:28] number of counters available for tracing */
-       drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
+       drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
        etm4_cs_lock(drvdata, csa);
        cpu_detect_trace_filtering(drvdata);
 }

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index c9c5fd6..3b604cd 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -165,6 +165,13 @@
 #define TRCIDR4_NUMCIDC_MASK                   GENMASK(27, 24)
 #define TRCIDR4_NUMVMIDC_MASK                  GENMASK(31, 28)
 
+#define TRCIDR5_NUMEXTIN_MASK                  GENMASK(8, 0)
+#define TRCIDR5_TRACEIDSIZE_MASK               GENMASK(21, 16)
+#define TRCIDR5_ATBTRIG                                BIT(22)
+#define TRCIDR5_LPOVERRIDE                     BIT(23)
+#define TRCIDR5_NUMSEQSTATE_MASK               GENMASK(27, 25)
+#define TRCIDR5_NUMCNTR_MASK                   GENMASK(30, 28)
+
 /*
  * System instructions to access ETM registers.
  * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions