signal dbus_buffer : std_logic_vector (dsize - 1 downto 0);
type dec_status is (reset0, reset1, reset2, reset3, reset4, reset5,
- fetch, exec,
- sei,
- txs,
- ldx1, ldx2, ldx3,
- jmp1, jmp2, jmp3, jmp4,
+ fetch, decode,
+ exec0, exec1, exec2, exec3, exec4, exec5,
unknown_stat);
signal cur_status : dec_status;
pc <= conv_std_logic_vector(16#8000#, asize);
end if;
+ ---micro code part.
if (set_clk'event and set_clk = '1') then
- d_print("~");
+ d_print("-");
---one byte instruction decoding.
case cur_status is
addr <= pc;
r_nw <= '1';
pc <= pc + 1;
- cur_status <= exec;
- when exec =>
- d_print(" exec and decode ", conv_integer(instruction));
- if instruction = conv_std_logic_vector(16#78#, dsize) then
- d_print(" sei");
- cur_status <= fetch;
- addr <= (others => 'Z');
- elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
- cur_status <= fetch;
- d_print(" ldx 0");
- addr <= pc;
- pc <= pc + 1;
- elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
- cur_status <= txs;
- d_print(" txs");
- addr <= pc;
- cur_status <= fetch;
- elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
- cur_status <= jmp1;
- d_print(" jmp 0");
- addr <= pc;
- pc <= pc + 1;
- else
- d_print(" unknown instruction. decode failure.");
- cur_status <= unknown_stat;
- end if;
+ cur_status <= decode;
+ when decode =>
+ null;
+ --operation impletemnted latter code.
- when ldx1 =>
- d_print(" ldx 1");
- when jmp1 =>
- d_print(" jmp 1");
- pc <= pc + 1;
- cur_status <= jmp2;
- when jmp2 =>
- d_print(" jmp 2");
- pc <= pc + 1;
- cur_status <= fetch;
+-- elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
+-- cur_status <= exec0;
+-- d_print(" ldx 0");
+-- addr <= pc;
+-- pc <= pc + 1;
+-- elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
+---- cur_status <= jmp1;
+---- d_print(" jmp 0");
+---- addr <= pc;
+---- pc <= pc + 1;
+-- else
+-- d_print(" unknown instruction. decode failure.");
+-- cur_status <= unknown_stat;
+-- end if;
+
+-- when ldx1 =>
+-- d_print(" ldx 1");
+-- when jmp1 =>
+-- d_print(" jmp 1");
+-- pc <= pc + 1;
+-- cur_status <= jmp2;
+-- when jmp2 =>
+-- d_print(" jmp 2");
+-- pc <= pc + 1;
+-- cur_status <= fetch;
when others =>
cur_status <= unknown_stat;
null;
end case;
+
+ ---instruction consists of aaabbbcc form.
+ if cur_status = decode then
+ d_print("inst:", instruction);
+ if instruction (1 downto 0) = "01" then
+ d_print("cc=01");
+
+ ---bbb part format
+ if instruction (4 downto 2) = "000" or
+ instruction (4 downto 2) = "001" or
+ instruction (4 downto 2) = "010" or
+ instruction (4 downto 2) = "011" or
+ instruction (4 downto 2) = "100" or
+ instruction (4 downto 2) = "101" or
+ instruction (4 downto 2) = "110" or
+ instruction (4 downto 2) = "111" then
+
+ if instruction (7 downto 5) = "000" then
+ d_print("ora");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("and");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("eor");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("adc");
+ elsif instruction (7 downto 5) = "100" then
+ d_print("sta");
+ elsif instruction (7 downto 5) = "101" then
+ d_print("lda");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cmp");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("sbc");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ end if;
+ else
+ ---else single byte instruction.
+ cur_status <= fetch;
+ addr <= (others => 'Z');
+ if instruction = conv_std_logic_vector(16#8a#, dsize) then
+ d_print("txa");
+ elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
+ d_print("txs");
+ elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
+ d_print("tax");
+ elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
+ d_print("tsx");
+ elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
+ d_print("dex");
+ elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
+ d_print("nop");
+ end if;
+ end if;
+ elsif instruction (1 downto 0) = "10" then
+ d_print("cc=10");
+
+ if instruction (7 downto 5) = "000" then
+ d_print("asl");
+ elsif instruction (7 downto 5) = "001" then
+ d_print("rol");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("lsr");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("ror");
+ elsif instruction (7 downto 5) = "100" then
+ d_print("stx");
+ elsif instruction (7 downto 5) = "101" then
+ d_print("ldx");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("dec");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("inc");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ end if;
+
+ elsif instruction (1 downto 0) = "00" then
+ d_print("cc=00 group...");
+
+ if instruction (4 downto 0) = "10000" then
+ ---conditional branch instruction..
+
+ ---bbb part format
+ elsif instruction (4 downto 2) = "000" or
+ instruction (4 downto 2) = "001" or
+ instruction (4 downto 2) = "011" or
+ instruction (4 downto 2) = "101" or
+ instruction (4 downto 2) = "111" then
+
+ if instruction (7 downto 5) = "001" then
+ d_print("bit");
+ elsif instruction (7 downto 5) = "010" then
+ d_print("jmp");
+ elsif instruction (7 downto 5) = "011" then
+ d_print("jmp");
+ elsif instruction (7 downto 5) = "100" then
+ d_print("sty");
+ elsif instruction (7 downto 5) = "101" then
+ d_print("ldy");
+ elsif instruction (7 downto 5) = "110" then
+ d_print("cpy");
+ elsif instruction (7 downto 5) = "111" then
+ d_print("cpx");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ end if;
+
+ else
+ ---else single byte instruction.
+ cur_status <= fetch;
+ addr <= (others => 'Z');
+ if instruction = conv_std_logic_vector(16#08#, dsize) then
+ d_print("php");
+ elsif instruction = conv_std_logic_vector(16#28#, dsize) then
+ d_print("plp");
+ elsif instruction = conv_std_logic_vector(16#48#, dsize) then
+ d_print("pha");
+ elsif instruction = conv_std_logic_vector(16#68#, dsize) then
+ d_print("pla");
+ elsif instruction = conv_std_logic_vector(16#88#, dsize) then
+ d_print("dey");
+ elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
+ d_print("tay");
+ elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
+ d_print("iny");
+ elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
+ d_print("inx");
+ elsif instruction = conv_std_logic_vector(16#18#, dsize) then
+ d_print("clc");
+ elsif instruction = conv_std_logic_vector(16#38#, dsize) then
+ d_print("sec");
+ elsif instruction = conv_std_logic_vector(16#58#, dsize) then
+ d_print("cli");
+ elsif instruction = conv_std_logic_vector(16#78#, dsize) then
+ d_print("sei");
+ elsif instruction = conv_std_logic_vector(16#98#, dsize) then
+ d_print("tya");
+ elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
+ d_print("clv");
+ elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
+ d_print("cld");
+ elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
+ d_print("sed");
+ else
+ assert false
+ report ("unknow instruction") severity failure;
+ end if;
+ end if;
+ end if;
+ end if;
end if;
if (trigger_clk'event and trigger_clk = '1') then
- d_print("_");
+ --d_print("_");
case cur_status is
- when exec =>
+ when decode =>
instruction <= d_io;
when others =>
null;
end if;
end process;
- operation_p : process (set_clk)
- begin
- ---instruction consists of aaabbbcc form.
- if set_clk'event and set_clk = '1' and cur_status = exec then
- d_print("inst:", instruction);
- if instruction (1 downto 0) = "01" then
- d_print("cc=01");
- if instruction = conv_std_logic_vector(16#8a#, dsize) then
- d_print("txa");
- elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
- d_print("txs");
- elsif instruction = conv_std_logic_vector(16#aa#, dsize) then
- d_print("tax");
- elsif instruction = conv_std_logic_vector(16#ba#, dsize) then
- d_print("tsx");
- elsif instruction = conv_std_logic_vector(16#ca#, dsize) then
- d_print("dex");
- elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
- d_print("nop");
- end if;
- elsif instruction (1 downto 0) = "10" then
- d_print("cc=10");
- elsif instruction (1 downto 0) = "00" then
- d_print("cc=00");
-
- if instruction = conv_std_logic_vector(16#08#, dsize) then
- d_print("php");
- elsif instruction = conv_std_logic_vector(16#28#, dsize) then
- d_print("plp");
- elsif instruction = conv_std_logic_vector(16#48#, dsize) then
- d_print("pha");
- elsif instruction = conv_std_logic_vector(16#68#, dsize) then
- d_print("pla");
- elsif instruction = conv_std_logic_vector(16#88#, dsize) then
- d_print("dey");
- elsif instruction = conv_std_logic_vector(16#a8#, dsize) then
- d_print("tay");
- elsif instruction = conv_std_logic_vector(16#c8#, dsize) then
- d_print("iny");
- elsif instruction = conv_std_logic_vector(16#e8#, dsize) then
- d_print("inx");
- elsif instruction = conv_std_logic_vector(16#18#, dsize) then
- d_print("clc");
- elsif instruction = conv_std_logic_vector(16#38#, dsize) then
- d_print("sec");
- elsif instruction = conv_std_logic_vector(16#58#, dsize) then
- d_print("cli");
- elsif instruction = conv_std_logic_vector(16#78#, dsize) then
- d_print("sei");
- elsif instruction = conv_std_logic_vector(16#98#, dsize) then
- d_print("tya");
- elsif instruction = conv_std_logic_vector(16#b8#, dsize) then
- d_print("clv");
- elsif instruction = conv_std_logic_vector(16#d8#, dsize) then
- d_print("cld");
- elsif instruction = conv_std_logic_vector(16#f8#, dsize) then
- d_print("sed");
- end if;
- end if;
- end if;
- end process;
end rtl;
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