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ARM: dts: imx6sx-sdb: Add PCIe support
authorFabio Estevam <fabio.estevam@nxp.com>
Tue, 21 Nov 2017 22:50:00 +0000 (20:50 -0200)
committerShawn Guo <shawnguo@kernel.org>
Tue, 26 Dec 2017 08:15:44 +0000 (16:15 +0800)
Add support for PCIe support.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6sx-sdb.dtsi

index d76b458..d57a41c 100644 (file)
                gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
        };
 
+       reg_pcie_gpio: regulator-pcie-gpio {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pcie_reg>;
+               regulator-name = "MPCIE_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        sound {
                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
                model = "wm8962-audio";
        };
 };
 
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
+       vpcie-supply = <&reg_pcie_gpio>;
+       status = "okay";
+};
+
 &lcdif1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lcd>;
                        >;
                };
 
+               pinctrl_pcie: pciegrp {
+                       fsl,pins = <
+                               MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
+                       >;
+               };
+
+               pinctrl_pcie_reg: pciereggrp {
+                       fsl,pins = <
+                               MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
+                       >;
+               };
+
                pinctrl_peri_3v3: peri3v3grp {
                        fsl,pins = <
                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000