drm/amdgpu/dce8: RMW hpd registers

No need to hard code the entire register to just
set/clear one bit.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index d0034e4..0245ed6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -326,9 +326,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 {
        struct drm_device *dev = adev->ddev;
        struct drm_connector *connector;
-       u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
-               (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
-               DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
+       u32 tmp;
 
        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -336,6 +334,8 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
                if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
                        continue;
 
+               tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+               tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
                WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
@@ -368,6 +368,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 {
        struct drm_device *dev = adev->ddev;
        struct drm_connector *connector;
+       u32 tmp;
 
        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -375,6 +376,8 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
                if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
                        continue;
 
+               tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+               tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
                WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 
                amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);