drm/i915/adl_p: Enable/disable loadgen sharing

Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.

BSpec: 55359

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-13-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b0ea081..eccbdd4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1459,6 +1459,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
                val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
                val &= ~DKL_TX_DP20BITMODE;
                intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+
+               if ((intel_crtc_has_dp_encoder(crtc_state) &&
+                    crtc_state->port_clock == 162000) ||
+                   (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+                    crtc_state->port_clock == 594000))
+                       val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
+               else
+                       val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c01de83..1ec0f0a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10825,6 +10825,7 @@ enum skl_power_gate {
                                                     _DKL_TX_DPCNTL1)
 
 #define _DKL_TX_DPCNTL2                                0x2C8
+#define  DKL_TX_LOADGEN_SHARING_PMD_DISABLE            REG_BIT(12)
 #define  DKL_TX_DP20BITMODE                            (1 << 2)
 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
                                                     _DKL_PHY1_BASE, \