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ASoC: SOF: Intel: add IP identifier
authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Thu, 14 Apr 2022 18:48:17 +0000 (13:48 -0500)
committerMark Brown <broonie@kernel.org>
Tue, 19 Apr 2022 11:03:46 +0000 (12:03 +0100)
This patch adds an IP identifier for each Intel platform. The
identifier will be used to select different code branches or
constants.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-16-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/bdw.c
sound/soc/sof/intel/byt.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/icl.c
sound/soc/sof/intel/pci-tng.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index 4762846..cb499f3 100644 (file)
@@ -77,5 +77,6 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .ssp_base_offset = APL_SSP_BASE_OFFSET,
        .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
 };
 EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 3449eec..73a2017 100644 (file)
@@ -637,6 +637,7 @@ static struct snd_sof_dsp_ops sof_bdw_ops = {
 static const struct sof_intel_dsp_desc bdw_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BROADWELL,
 };
 
 static const struct sof_dev_desc sof_acpi_broadwell_desc = {
index 3db125d..08376e8 100644 (file)
@@ -295,6 +295,7 @@ static struct snd_sof_dsp_ops sof_byt_ops = {
 static const struct sof_intel_dsp_desc byt_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BAYTRAIL,
 };
 
 /* cherrytrail and braswell ops */
@@ -378,6 +379,7 @@ static struct snd_sof_dsp_ops sof_cht_ops = {
 static const struct sof_intel_dsp_desc cht_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_BAYTRAIL,
 };
 
 /* BYTCR uses different IRQ index */
index 86b6834..f5bac91 100644 (file)
@@ -297,6 +297,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_1_8,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -325,5 +326,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 2e4d371..8dd5626 100644 (file)
@@ -142,5 +142,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_0,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index ca313c7..14f1152 100644 (file)
@@ -210,6 +210,7 @@ struct snd_sof_dsp_ops sof_tng_ops = {
 const struct sof_intel_dsp_desc tng_chip_info = {
        .cores_num = 1,
        .host_managed_cores_mask = 1,
+       .hw_ip_version = SOF_INTEL_TANGIER,
 };
 
 static const struct sof_dev_desc tng_desc = {
index 3eb0994..1fd7b48 100644 (file)
 #ifndef __SOF_INTEL_SHIM_H
 #define __SOF_INTEL_SHIM_H
 
+enum sof_intel_hw_ip_version {
+       SOF_INTEL_TANGIER,
+       SOF_INTEL_BAYTRAIL,
+       SOF_INTEL_BROADWELL,
+       SOF_INTEL_CAVS_1_5,     /* SkyLake, KabyLake, AmberLake */
+       SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
+       SOF_INTEL_CAVS_1_8,     /* CannonLake, CometLake, CoffeeLake */
+       SOF_INTEL_CAVS_2_0,     /* IceLake, JasperLake */
+       SOF_INTEL_CAVS_2_5,     /* TigerLake, AlderLake */
+};
+
 /*
  * SHIM registers for BYT, BSW, CHT, BDW
  */
@@ -171,6 +182,7 @@ struct sof_intel_dsp_desc {
        u32 sdw_shim_base;
        u32 sdw_alh_base;
        u32 quirks;
+       enum sof_intel_hw_ip_version hw_ip_version;
        bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
        bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
 };
index 32d7e15..8165713 100644 (file)
@@ -113,6 +113,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -134,6 +135,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -155,6 +157,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -176,5 +179,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .sdw_alh_base = SDW_ALH_BASE,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
+       .hw_ip_version = SOF_INTEL_CAVS_2_5,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);