Try to work around possible bugs in version of Shpinx on buildserver.

Builds sucessfully with Sphinx v1.5.5

Differential Revision: https://reviews.llvm.org/D33736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304853 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst
index f6dcfc6..ae7fbe2 100644 (file)
--- a/docs/AMDGPUUsage.rst
+++ b/docs/AMDGPUUsage.rst
@@ -1468,9 +1468,9 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
   .. table:: compute_pgm_rsrc1 for GFX6-GFX9
      :name: amdgpu-amdhsa-compute_pgm_rsrc1_t-gfx6-gfx9-table
 
-     ======= ======= =============================== ===========================
+     ======= ======= =============================== ===========================================================================
      Bits    Size    Field Name                      Description
-     ======= ======= =============================== ===========================
+     ======= ======= =============================== ===========================================================================
      5:0     6 bits  granulated_workitem_vgpr_count  Number of vector registers
                                                      used by each work-item,
                                                      granularity is device
@@ -1626,16 +1626,16 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
                                                      ``COMPUTE_PGM_RSRC1.CDBG_USER``.
      31:26   6 bits                                  Reserved. Must be 0.
      32      **Total size 4 bytes**
-     ======= ===================================================================
+     ======= ===================================================================================================================
 
 ..
 
   .. table:: compute_pgm_rsrc2 for GFX6-GFX9
      :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table
 
-     ======= ======= =============================== ===========================
+     ======= ======= =============================== ===========================================================================
      Bits    Size    Field Name                      Description
-     ======= ======= =============================== ===========================
+     ======= ======= =============================== ===========================================================================
      0       1 bit   enable_sgpr_private_segment     Enable the setup of the
                      _wave_offset                    SGPR wave scratch offset
                                                      system register (see
@@ -1783,7 +1783,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
                                                      only)
      31      1 bit                                   Reserved. Must be 0.
      32      **Total size 4 bytes.**
-     ======= ===================================================================
+     ======= ===================================================================================================================
 
 ..