#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
+#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
platform_driver_unregister(&gcc_falcon_driver);
}
module_exit(gcc_falcon_exit);
+
+/* Debug Mux for measure */
+static struct measure_clk_data debug_mux_priv = {
+ .xo_div4_cbcr = 0x43008,
+ .ctl_reg = 0x62004,
+ .status_reg = 0x62008,
+};
+
+static const char *const debug_mux_parent_names[] = {
+ "snoc_clk",
+ "cnoc_clk",
+ "cnoc_periph",
+ "bimc_clk",
+ "ce1_clk",
+ "ipa_clk",
+ "gcc_aggre2_ufs_axi_clk",
+ "gcc_aggre2_usb3_axi_clk",
+ "gcc_bimc_gfx_clk",
+ "gcc_bimc_hmss_axi_clk",
+ "gcc_bimc_mss_q6_axi_clk",
+ "gcc_blsp1_ahb_clk",
+ "gcc_blsp1_qup1_i2c_apps_clk",
+ "gcc_blsp1_qup1_spi_apps_clk",
+ "gcc_blsp1_qup2_i2c_apps_clk",
+ "gcc_blsp1_qup2_spi_apps_clk",
+ "gcc_blsp1_qup3_i2c_apps_clk",
+ "gcc_blsp1_qup3_spi_apps_clk",
+ "gcc_blsp1_qup4_i2c_apps_clk",
+ "gcc_blsp1_qup4_spi_apps_clk",
+ "gcc_blsp1_uart1_apps_clk",
+ "gcc_blsp1_uart2_apps_clk",
+ "gcc_blsp2_ahb_clk",
+ "gcc_blsp2_qup1_i2c_apps_clk",
+ "gcc_blsp2_qup1_spi_apps_clk",
+ "gcc_blsp2_qup2_i2c_apps_clk",
+ "gcc_blsp2_qup2_spi_apps_clk",
+ "gcc_blsp2_qup3_i2c_apps_clk",
+ "gcc_blsp2_qup3_spi_apps_clk",
+ "gcc_blsp2_qup4_i2c_apps_clk",
+ "gcc_blsp2_qup4_spi_apps_clk",
+ "gcc_blsp2_uart1_apps_clk",
+ "gcc_blsp2_uart2_apps_clk",
+ "gcc_boot_rom_ahb_clk",
+ "gcc_ce1_ahb_m_clk",
+ "gcc_ce1_axi_m_clk",
+ "gcc_cfg_noc_usb2_axi_clk",
+ "gcc_cfg_noc_usb3_axi_clk",
+ "gcc_dcc_ahb_clk",
+ "gcc_gp1_clk",
+ "gcc_gp2_clk",
+ "gcc_gp3_clk",
+ "gcc_gpu_bimc_gfx_clk",
+ "gcc_gpu_bimc_gfx_src_clk",
+ "gcc_gpu_cfg_ahb_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gcc_hmss_ahb_clk",
+ "gcc_hmss_dvm_bus_clk",
+ "gcc_hmss_rbcpr_clk",
+ "gcc_mmss_noc_cfg_ahb_clk",
+ "gcc_mmss_sys_noc_axi_clk",
+ "gcc_mss_cfg_ahb_clk",
+ "gcc_mss_mnoc_bimc_axi_clk",
+ "gcc_mss_q6_bimc_axi_clk",
+ "gcc_mss_snoc_axi_clk",
+ "gcc_pdm2_clk",
+ "gcc_pdm_ahb_clk",
+ "gcc_prng_ahb_clk",
+ "gcc_qspi_ahb_clk",
+ "gcc_qspi_ser_clk",
+ "gcc_sdcc1_ahb_clk",
+ "gcc_sdcc1_apps_clk",
+ "gcc_sdcc1_ice_core_clk",
+ "gcc_sdcc2_ahb_clk",
+ "gcc_sdcc2_apps_clk",
+ "gcc_ufs_ahb_clk",
+ "gcc_ufs_axi_clk",
+ "gcc_ufs_ice_core_clk",
+ "gcc_ufs_phy_aux_clk",
+ "gcc_ufs_unipro_core_clk",
+ "gcc_usb20_master_clk",
+ "gcc_usb20_mock_utmi_clk",
+ "gcc_usb20_sleep_clk",
+ "gcc_usb30_master_clk",
+ "gcc_usb30_mock_utmi_clk",
+ "gcc_usb30_sleep_clk",
+ "gcc_usb3_phy_aux_clk",
+ "gcc_usb_phy_cfg_ahb2phy_clk",
+ "gcc_ufs_rx_symbol_0_clk",
+ "gcc_ufs_rx_symbol_1_clk",
+ "gcc_ufs_tx_symbol_0_clk",
+ "gcc_usb3_phy_pipe_clk",
+ "mmss_bimc_smmu_ahb_clk",
+ "mmss_bimc_smmu_axi_clk",
+ "mmss_camss_ahb_clk",
+ "mmss_camss_cci_ahb_clk",
+ "mmss_camss_cci_clk",
+ "mmss_camss_cphy_csid0_clk",
+ "mmss_camss_cphy_csid1_clk",
+ "mmss_camss_cphy_csid2_clk",
+ "mmss_camss_cphy_csid3_clk",
+ "mmss_camss_cpp_ahb_clk",
+ "mmss_camss_cpp_axi_clk",
+ "mmss_camss_cpp_clk",
+ "mmss_camss_cpp_vbif_ahb_clk",
+ "mmss_camss_csi0_ahb_clk",
+ "mmss_camss_csi0_clk",
+ "mmss_camss_csi0phytimer_clk",
+ "mmss_camss_csi0pix_clk",
+ "mmss_camss_csi0rdi_clk",
+ "mmss_camss_csi1_ahb_clk",
+ "mmss_camss_csi1_clk",
+ "mmss_camss_csi1phytimer_clk",
+ "mmss_camss_csi1pix_clk",
+ "mmss_camss_csi1rdi_clk",
+ "mmss_camss_csi2_ahb_clk",
+ "mmss_camss_csi2_clk",
+ "mmss_camss_csi2phytimer_clk",
+ "mmss_camss_csi2pix_clk",
+ "mmss_camss_csi2rdi_clk",
+ "mmss_camss_csi3_ahb_clk",
+ "mmss_camss_csi3_clk",
+ "mmss_camss_csi3pix_clk",
+ "mmss_camss_csi3rdi_clk",
+ "mmss_camss_csi_vfe0_clk",
+ "mmss_camss_csi_vfe1_clk",
+ "mmss_camss_csiphy0_clk",
+ "mmss_camss_csiphy1_clk",
+ "mmss_camss_csiphy2_clk",
+ "mmss_camss_gp0_clk",
+ "mmss_camss_gp1_clk",
+ "mmss_camss_ispif_ahb_clk",
+ "mmss_camss_jpeg0_clk",
+ "mmss_camss_jpeg_ahb_clk",
+ "mmss_camss_jpeg_axi_clk",
+ "mmss_camss_mclk0_clk",
+ "mmss_camss_mclk1_clk",
+ "mmss_camss_mclk2_clk",
+ "mmss_camss_mclk3_clk",
+ "mmss_camss_micro_ahb_clk",
+ "mmss_camss_top_ahb_clk",
+ "mmss_camss_vfe0_ahb_clk",
+ "mmss_camss_vfe0_clk",
+ "mmss_camss_vfe0_stream_clk",
+ "mmss_camss_vfe1_ahb_clk",
+ "mmss_camss_vfe1_clk",
+ "mmss_camss_vfe1_stream_clk",
+ "mmss_camss_vfe_vbif_ahb_clk",
+ "mmss_camss_vfe_vbif_axi_clk",
+ "mmss_csiphy_ahb2crif_clk",
+ "mmss_mdss_ahb_clk",
+ "mmss_mdss_axi_clk",
+ "mmss_mdss_byte0_clk",
+ "mmss_mdss_byte0_intf_clk",
+ "mmss_mdss_byte1_clk",
+ "mmss_mdss_byte1_intf_clk",
+ "mmss_mdss_dp_aux_clk",
+ "mmss_mdss_dp_crypto_clk",
+ "mmss_mdss_dp_gtc_clk",
+ "mmss_mdss_dp_link_clk",
+ "mmss_mdss_dp_link_intf_clk",
+ "mmss_mdss_dp_pixel_clk",
+ "mmss_mdss_esc0_clk",
+ "mmss_mdss_esc1_clk",
+ "mmss_mdss_hdmi_dp_ahb_clk",
+ "mmss_mdss_mdp_clk",
+ "mmss_mdss_pclk0_clk",
+ "mmss_mdss_pclk1_clk",
+ "mmss_mdss_rot_clk",
+ "mmss_mdss_vsync_clk",
+ "mmss_misc_ahb_clk",
+ "mmss_misc_cxo_clk",
+ "mmss_mnoc_ahb_clk",
+ "mmss_snoc_dvm_axi_clk",
+ "mmss_video_ahb_clk",
+ "mmss_video_axi_clk",
+ "mmss_video_core_clk",
+ "mmss_video_subcore0_clk",
+ "gpucc_gfx3d_clk",
+ "gpucc_rbbmtimer_clk",
+ "gpucc_rbcpr_clk",
+ "pwrcl_clk",
+ "perfcl_clk",
+};
+
+static struct clk_debug_mux gcc_debug_mux = {
+ .priv = &debug_mux_priv,
+ .en_mask = BIT(16),
+ .mask = 0x3FF,
+ MUX_SRC_LIST(
+ { "snoc_clk", 0x000 },
+ { "cnoc_clk", 0x00E },
+ { "cnoc_periph_clk", 0x198 },
+ { "bimc_clk", 0x14E },
+ { "ce1_clk", 0x097 },
+ { "ipa_clk", 0x11b },
+ { "gcc_aggre2_ufs_axi_clk", 0x10B },
+ { "gcc_aggre2_usb3_axi_clk", 0x10A },
+ { "gcc_bimc_gfx_clk", 0x0AC },
+ { "gcc_bimc_hmss_axi_clk", 0x0BB },
+ { "gcc_bimc_mss_q6_axi_clk", 0x0A3 },
+ { "gcc_blsp1_ahb_clk", 0x04A },
+ { "gcc_blsp1_qup1_i2c_apps_clk", 0x04D },
+ { "gcc_blsp1_qup1_spi_apps_clk", 0x04C },
+ { "gcc_blsp1_qup2_i2c_apps_clk", 0x051 },
+ { "gcc_blsp1_qup2_spi_apps_clk", 0x050 },
+ { "gcc_blsp1_qup3_i2c_apps_clk", 0x055 },
+ { "gcc_blsp1_qup3_spi_apps_clk", 0x054 },
+ { "gcc_blsp1_qup4_i2c_apps_clk", 0x059 },
+ { "gcc_blsp1_qup4_spi_apps_clk", 0x058 },
+ { "gcc_blsp1_uart1_apps_clk", 0x04E },
+ { "gcc_blsp1_uart2_apps_clk", 0x052 },
+ { "gcc_blsp2_ahb_clk", 0x05E },
+ { "gcc_blsp2_qup1_i2c_apps_clk", 0x061 },
+ { "gcc_blsp2_qup1_spi_apps_clk", 0x060 },
+ { "gcc_blsp2_qup2_i2c_apps_clk", 0x065 },
+ { "gcc_blsp2_qup2_spi_apps_clk", 0x064 },
+ { "gcc_blsp2_qup3_i2c_apps_clk", 0x069 },
+ { "gcc_blsp2_qup3_spi_apps_clk", 0x068 },
+ { "gcc_blsp2_qup4_i2c_apps_clk", 0x06D },
+ { "gcc_blsp2_qup4_spi_apps_clk", 0x06C },
+ { "gcc_blsp2_uart1_apps_clk", 0x062 },
+ { "gcc_blsp2_uart2_apps_clk", 0x066 },
+ { "gcc_boot_rom_ahb_clk", 0x07A },
+ { "gcc_ce1_ahb_m_clk", 0x099 },
+ { "gcc_ce1_axi_m_clk", 0x098 },
+ { "gcc_cfg_noc_usb2_axi_clk", 0x168 },
+ { "gcc_cfg_noc_usb3_axi_clk", 0x014 },
+ { "gcc_dcc_ahb_clk", 0x119 },
+ { "gcc_gp1_clk", 0x0DF },
+ { "gcc_gp2_clk", 0x0E0 },
+ { "gcc_gp3_clk", 0x0E1 },
+ { "gcc_gpu_bimc_gfx_clk", 0x13F },
+ { "gcc_gpu_bimc_gfx_src_clk", 0x13E },
+ { "gcc_gpu_cfg_ahb_clk", 0x13B },
+ { "gcc_gpu_snoc_dvm_gfx_clk", 0x141 },
+ { "gcc_hmss_ahb_clk", 0x0BA },
+ { "gcc_hmss_dvm_bus_clk", 0x0BF },
+ { "gcc_hmss_rbcpr_clk", 0x0BC },
+ { "gcc_mmss_noc_cfg_ahb_clk", 0x020 },
+ { "gcc_mmss_sys_noc_axi_clk", 0x01F },
+ { "gcc_mss_cfg_ahb_clk", 0x11F },
+ { "gcc_mss_mnoc_bimc_axi_clk", 0x120 },
+ { "gcc_mss_q6_bimc_axi_clk", 0x124 },
+ { "gcc_mss_snoc_axi_clk", 0x123 },
+ { "gcc_pdm2_clk", 0x074 },
+ { "gcc_pdm_ahb_clk", 0x072 },
+ { "gcc_prng_ahb_clk", 0x075 },
+ { "gcc_qspi_ahb_clk", 0x172 },
+ { "gcc_qspi_ser_clk", 0x173 },
+ { "gcc_sdcc1_ahb_clk", 0x16E },
+ { "gcc_sdcc1_apps_clk", 0x16D },
+ { "gcc_sdcc1_ice_core_clk", 0x16F },
+ { "gcc_sdcc2_ahb_clk", 0x047 },
+ { "gcc_sdcc2_apps_clk", 0x046 },
+ { "gcc_ufs_ahb_clk", 0x0EB },
+ { "gcc_ufs_axi_clk", 0x0EA },
+ { "gcc_ufs_ice_core_clk", 0x0F1 },
+ { "gcc_ufs_phy_aux_clk", 0x0F2 },
+ { "gcc_ufs_unipro_core_clk", 0x0F0 },
+ { "gcc_usb20_master_clk", 0x169 },
+ { "gcc_usb20_mock_utmi_clk", 0x16B },
+ { "gcc_usb20_sleep_clk", 0x16A },
+ { "gcc_usb30_master_clk", 0x03C },
+ { "gcc_usb30_mock_utmi_clk", 0x03E },
+ { "gcc_usb30_sleep_clk", 0x03D },
+ { "gcc_usb3_phy_aux_clk", 0x03F },
+ { "gcc_usb_phy_cfg_ahb2phy_clk", 0x045 },
+ { "gcc_ufs_rx_symbol_0_clk", 0x0ED },
+ { "gcc_ufs_rx_symbol_1_clk", 0x162 },
+ { "gcc_ufs_tx_symbol_0_clk", 0x0EC },
+ { "gcc_usb3_phy_pipe_clk", 0x040 },
+ { "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C },
+ { "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D },
+ { "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 },
+ { "mmss_camss_cci_ahb_clk", 0x22, MMCC, 0x02E },
+ { "mmss_camss_cci_clk", 0x22, MMCC, 0x02D },
+ { "mmss_camss_cphy_csid0_clk", 0x22, MMCC, 0x08D },
+ { "mmss_camss_cphy_csid1_clk", 0x22, MMCC, 0x08E },
+ { "mmss_camss_cphy_csid2_clk", 0x22, MMCC, 0x08F },
+ { "mmss_camss_cphy_csid3_clk", 0x22, MMCC, 0x090 },
+ { "mmss_camss_cpp_ahb_clk", 0x22, MMCC, 0x03B },
+ { "mmss_camss_cpp_axi_clk", 0x22, MMCC, 0x07A },
+ { "mmss_camss_cpp_clk", 0x22, MMCC, 0x03A },
+ { "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC, 0x073 },
+ { "mmss_camss_csi0_ahb_clk", 0x22, MMCC, 0x042 },
+ { "mmss_camss_csi0_clk", 0x22, MMCC, 0x041 },
+ { "mmss_camss_csi0phytimer_clk", 0x22, MMCC, 0x02F },
+ { "mmss_camss_csi0pix_clk", 0x22, MMCC, 0x045 },
+ { "mmss_camss_csi0rdi_clk", 0x22, MMCC, 0x044 },
+ { "mmss_camss_csi1_ahb_clk", 0x22, MMCC, 0x047 },
+ { "mmss_camss_csi1_clk", 0x22, MMCC, 0x046 },
+ { "mmss_camss_csi1phytimer_clk", 0x22, MMCC, 0x030 },
+ { "mmss_camss_csi1pix_clk", 0x22, MMCC, 0x04A },
+ { "mmss_camss_csi1rdi_clk", 0x22, MMCC, 0x049 },
+ { "mmss_camss_csi2_ahb_clk", 0x22, MMCC, 0x04C },
+ { "mmss_camss_csi2_clk", 0x22, MMCC, 0x04B },
+ { "mmss_camss_csi2phytimer_clk", 0x22, MMCC, 0x031 },
+ { "mmss_camss_csi2pix_clk", 0x22, MMCC, 0x04F },
+ { "mmss_camss_csi2rdi_clk", 0x22, MMCC, 0x04E },
+ { "mmss_camss_csi3_ahb_clk", 0x22, MMCC, 0x051 },
+ { "mmss_camss_csi3_clk", 0x22, MMCC, 0x050 },
+ { "mmss_camss_csi3pix_clk", 0x22, MMCC, 0x054 },
+ { "mmss_camss_csi3rdi_clk", 0x22, MMCC, 0x053 },
+ { "mmss_camss_csi_vfe0_clk", 0x22, MMCC, 0x03F },
+ { "mmss_camss_csi_vfe1_clk", 0x22, MMCC, 0x040 },
+ { "mmss_camss_csiphy0_clk", 0x22, MMCC, 0x043 },
+ { "mmss_camss_csiphy1_clk", 0x22, MMCC, 0x085 },
+ { "mmss_camss_csiphy2_clk", 0x22, MMCC, 0x088 },
+ { "mmss_camss_gp0_clk", 0x22, MMCC, 0x027 },
+ { "mmss_camss_gp1_clk", 0x22, MMCC, 0x028 },
+ { "mmss_camss_ispif_ahb_clk", 0x22, MMCC, 0x033 },
+ { "mmss_camss_jpeg0_clk", 0x22, MMCC, 0x032 },
+ { "mmss_camss_jpeg_ahb_clk", 0x22, MMCC, 0x035 },
+ { "mmss_camss_jpeg_axi_clk", 0x22, MMCC, 0x036 },
+ { "mmss_camss_mclk0_clk", 0x22, MMCC, 0x029 },
+ { "mmss_camss_mclk1_clk", 0x22, MMCC, 0x02A },
+ { "mmss_camss_mclk2_clk", 0x22, MMCC, 0x02B },
+ { "mmss_camss_mclk3_clk", 0x22, MMCC, 0x02C },
+ { "mmss_camss_micro_ahb_clk", 0x22, MMCC, 0x026 },
+ { "mmss_camss_top_ahb_clk", 0x22, MMCC, 0x025 },
+ { "mmss_camss_vfe0_ahb_clk", 0x22, MMCC, 0x086 },
+ { "mmss_camss_vfe0_clk", 0x22, MMCC, 0x038 },
+ { "mmss_camss_vfe0_stream_clk", 0x22, MMCC, 0x071 },
+ { "mmss_camss_vfe1_ahb_clk", 0x22, MMCC, 0x087 },
+ { "mmss_camss_vfe1_clk", 0x22, MMCC, 0x039 },
+ { "mmss_camss_vfe1_stream_clk", 0x22, MMCC, 0x072 },
+ { "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC, 0x03C },
+ { "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC, 0x03D },
+ { "mmss_csiphy_ahb2crif_clk", 0x22, MMCC, 0x0B8 },
+ { "mmss_mdss_ahb_clk", 0x22, MMCC, 0x022 },
+ { "mmss_mdss_axi_clk", 0x22, MMCC, 0x024 },
+ { "mmss_mdss_byte0_clk", 0x22, MMCC, 0x01E },
+ { "mmss_mdss_byte0_intf_clk", 0x22, MMCC, 0x0AD },
+ { "mmss_mdss_byte1_clk", 0x22, MMCC, 0x01F },
+ { "mmss_mdss_byte1_intf_clk", 0x22, MMCC, 0x0B6 },
+ { "mmss_mdss_dp_aux_clk", 0x22, MMCC, 0x09C },
+ { "mmss_mdss_dp_crypto_clk", 0x22, MMCC, 0x09A },
+ { "mmss_mdss_dp_gtc_clk", 0x22, MMCC, 0x09D },
+ { "mmss_mdss_dp_link_clk", 0x22, MMCC, 0x098 },
+ { "mmss_mdss_dp_link_intf_clk", 0x22, MMCC, 0x099 },
+ { "mmss_mdss_dp_pixel_clk", 0x22, MMCC, 0x09B },
+ { "mmss_mdss_esc0_clk", 0x22, MMCC, 0x020 },
+ { "mmss_mdss_esc1_clk", 0x22, MMCC, 0x021 },
+ { "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC, 0x023 },
+ { "mmss_mdss_mdp_clk", 0x22, MMCC, 0x014 },
+ { "mmss_mdss_pclk0_clk", 0x22, MMCC, 0x016 },
+ { "mmss_mdss_pclk1_clk", 0x22, MMCC, 0x017 },
+ { "mmss_mdss_rot_clk", 0x22, MMCC, 0x012 },
+ { "mmss_mdss_vsync_clk", 0x22, MMCC, 0x01C },
+ { "mmss_misc_ahb_clk", 0x22, MMCC, 0x003 },
+ { "mmss_misc_cxo_clk", 0x22, MMCC, 0x077 },
+ { "mmss_mnoc_ahb_clk", 0x22, MMCC, 0x001 },
+ { "mmss_snoc_dvm_axi_clk", 0x22, MMCC, 0x013 },
+ { "mmss_video_ahb_clk", 0x22, MMCC, 0x011 },
+ { "mmss_video_axi_clk", 0x22, MMCC, 0x00F },
+ { "mmss_video_core_clk", 0x22, MMCC, 0x00E },
+ { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A },
+ { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 },
+ { "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 },
+ { "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 },
+ { "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF },
+ { "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF },
+ ),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_debug_mux",
+ .ops = &clk_debug_mux_ops,
+ .parent_names = debug_mux_parent_names,
+ .num_parents = ARRAY_SIZE(debug_mux_parent_names),
+ .flags = CLK_IS_MEASURE,
+ },
+};
+
+static const struct of_device_id clk_debug_match_table[] = {
+ { .compatible = "qcom,gcc-debug-msmfalcon" },
+ {}
+};
+
+static int clk_debug_falcon_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct clk *clk;
+ int ret = 0, count;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbg_offset");
+ if (!res) {
+ dev_err(&pdev->dev, "Failed to get debug offset.\n");
+ return -EINVAL;
+ }
+ gcc_debug_mux.debug_offset = res->start;
+
+ clk = devm_clk_get(&pdev->dev, "xo_clk_src");
+ if (IS_ERR(clk)) {
+ if (PTR_ERR(clk) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Unable to get xo clock\n");
+ return PTR_ERR(clk);
+ }
+
+ debug_mux_priv.cxo = clk;
+
+ ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count",
+ &count);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Num of debug clock controller not specified\n");
+ return ret;
+ }
+
+ if (!count) {
+ dev_err(&pdev->dev, "Count of CC cannot be zero\n");
+ return -EINVAL;
+ }
+
+ gcc_debug_mux.num_parent_regmap = count;
+
+ gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev,
+ sizeof(struct regmap *) * count, GFP_KERNEL);
+ if (!gcc_debug_mux.regmap)
+ return -ENOMEM;
+
+ if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) {
+ gcc_debug_mux.regmap[GCC] =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "qcom,gcc");
+ if (IS_ERR(gcc_debug_mux.regmap[GCC]))
+ return PTR_ERR(gcc_debug_mux.regmap[GCC]);
+ }
+
+ if (of_get_property(pdev->dev.of_node, "qcom,cpu", NULL)) {
+ gcc_debug_mux.regmap[CPU] =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "qcom,cpu");
+ if (IS_ERR(gcc_debug_mux.regmap[CPU]))
+ return PTR_ERR(gcc_debug_mux.regmap[CPU]);
+ }
+
+ if (of_get_property(pdev->dev.of_node, "qcom,mmss", NULL)) {
+ gcc_debug_mux.regmap[MMCC] =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "qcom,mmss");
+ if (IS_ERR(gcc_debug_mux.regmap[MMCC]))
+ return PTR_ERR(gcc_debug_mux.regmap[MMCC]);
+
+ /* Clear the DBG_CLK_DIV bits of the MMSS debug register */
+ regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0,
+ 0x60000, 0x0);
+ }
+
+ if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) {
+ gcc_debug_mux.regmap[GPU] =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "qcom,gpu");
+ if (IS_ERR(gcc_debug_mux.regmap[GPU]))
+ return PTR_ERR(gcc_debug_mux.regmap[GPU]);
+
+ /* Clear the DBG_CLK_DIV bits of the GPU debug register */
+ regmap_update_bits(gcc_debug_mux.regmap[GPU], 0x0,
+ 0x60000, 0x0);
+ }
+
+ clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "Unable to register GCC debug mux\n");
+ return PTR_ERR(clk);
+ }
+
+ dev_info(&pdev->dev, "Registered debug mux successfully\n");
+
+ return ret;
+}
+
+static struct platform_driver clk_debug_driver = {
+ .probe = clk_debug_falcon_probe,
+ .driver = {
+ .name = "gcc-debug-msmfalcon",
+ .of_match_table = clk_debug_match_table,
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init clk_debug_falcon_init(void)
+{
+ return platform_driver_register(&clk_debug_driver);
+}
+fs_initcall(clk_debug_falcon_init);
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