P_GPLL4,
};
-static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
-};
-
-static const char * const gcc_xo_gpll0[] = {
- "xo",
- "gpll0",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL4, 5 },
-};
-
-static const char * const gcc_xo_gpll0_gpll4[] = {
- "xo",
- "gpll0",
- "gpll4",
-};
-
-static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data)
- {
- .name = "xo",
- .parent_names = (const char *[]) { "xo_board" },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
static struct clk_alpha_pll gpll0_early = {
- .offset = 0x00000,
+ .offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gpll0_early",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
- .offset = 0x00000,
+ .offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]) { "gpll0_early" },
.num_parents = 1,
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gpll4_early",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x1dc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_names = (const char *[]) { "gpll4_early" },
.num_parents = 1,
},
};
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .fw_name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .fw_name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp2_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp3_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_0_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.cmd_rcgr = 0x1adc,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_1_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.cmd_rcgr = 0x1b5c,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
+ .parent_data = gcc_xo_gpll0_gpll4,
.num_parents = 3,
.ops = &clk_rcg2_floor_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.cmd_rcgr = 0x1414,
.hid_width = 5,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hs_system_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0648,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup1_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0644,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup1_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x06c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup2_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x06c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup2_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0748,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup3_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0744,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup3_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x07c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup4_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x07c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup4_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0848,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup5_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0844,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup5_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x08c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup6_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x08c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup6_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0684,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0784,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0804,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0884,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart5_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0904,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart6_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0988,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup1_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0984,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup1_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0a08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup2_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0a04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup2_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0a88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup3_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0a84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup3_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0b08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup4_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0b04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup4_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0b88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup5_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0b84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup5_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0c08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup6_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0c04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup6_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x09c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0a44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0ac4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0b44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0bc4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart5_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0c44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart6_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1900,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]) {
- "gp1_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1940,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]) {
- "gp2_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1980,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]) {
- "gp3_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0280,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0284,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1ad4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
- .parent_names = (const char *[]) {
- "pcie_0_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1ad0,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1acc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1ad8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
- .parent_names = (const char *[]) {
- "pcie_0_pipe_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1ac8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
- .parent_names = (const char *[]) {
- "pcie_1_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1b50,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1b58,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
- .parent_names = (const char *[]) {
- "pcie_1_pipe_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1b48,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0ccc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_names = (const char *[]) {
- "pdm2_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0cc4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x04c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x04c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
.clkr = {
.enable_reg = 0x0508,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
.clkr = {
.enable_reg = 0x0504,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0548,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
.clkr = {
.enable_reg = 0x0544,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0588,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
.clkr = {
.enable_reg = 0x0584,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1d7c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x03fc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
- .parent_names = (const char *[]) {
- "usb30_master_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0d84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0d88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
- .parent_names = (const char *[]) {
- "tsif_ref_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1d4c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1d48,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1d54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1d60,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1d64,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1d50,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1d58,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x1d5c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x04ac,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb2_hs_phy_sleep_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep",
+ .name = "sleep"
+ },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
.clkr = {
.enable_reg = 0x03c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
- .parent_names = (const char *[]) {
- "usb30_master_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x03d0,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
- .parent_names = (const char *[]) {
- "usb30_mock_utmi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x03cc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep",
+ .name = "sleep"
+ },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
.clkr = {
.enable_reg = 0x1408,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
- .parent_names = (const char *[]) {
- "usb3_phy_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x0488,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.ops = &clk_branch2_ops,
},
.clkr = {
.enable_reg = 0x0484,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_names = (const char *[]) {
- "usb_hs_system_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
.clkr = {
.enable_reg = 0x1a84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
static int gcc_msm8994_probe(struct platform_device *pdev)
{
- struct device *dev = &pdev->dev;
- struct clk *clk;
-
- clk = devm_clk_register(dev, &xo.hw);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
}