The 'kvm_sw_tlb' and 'tlb_dirty' fields introduced in commit
93dd5e852c ("kvm: ppc: booke206: use MMU API") are specific
to KVM and shouldn't be accessed when it is not available.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <
20230624192645.13680-1-philmd@linaro.org>
tlb->mas7_3 = 0;
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+#ifdef CONFIG_KVM
env->tlb_dirty = true;
+#endif
}
static void ppce500_cpu_reset_sec(void *opaque)
tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
tlb->mas7_3 = pa & TARGET_PAGE_MASK;
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+#ifdef CONFIG_KVM
env->tlb_dirty = true;
+#endif
}
static void spin_kick(CPUState *cs, run_on_cpu_data data)
int nb_pids; /* Number of available PID registers */
int tlb_type; /* Type of TLB we're dealing with */
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
+#ifdef CONFIG_KVM
bool tlb_dirty; /* Set to non-zero when modifying TLB */
bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
+#endif /* CONFIG_KVM */
uint32_t tlb_need_flush; /* Delayed flush needed */
#define TLB_NEED_LOCAL_FLUSH 0x1
#define TLB_NEED_GLOBAL_FLUSH 0x2
ppcemb_tlb_t *entry;
int i;
+#ifdef CONFIG_KVM
if (kvm_enabled() && !env->kvm_sw_tlb) {
qemu_printf("Cannot access KVM TLB\n");
return;
}
+#endif
qemu_printf("\nTLB:\n");
qemu_printf("Effective Physical Size PID Prot "
int offset = 0;
int i;
+#ifdef CONFIG_KVM
if (kvm_enabled() && !env->kvm_sw_tlb) {
qemu_printf("Cannot access KVM TLB\n");
return;
}
+#endif
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
int size = booke206_tlb_size(env, i);