[NISTC_AI_CMD1_REG] = { 0x110, 2 },
[NISTC_AO_CMD1_REG] = { 0x112, 2 },
/*
- * DIO_Output_Register maps to:
+ * NISTC_DIO_OUT_REG maps to:
* { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
*/
- [DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
+ [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
[AI_Mode_1_Register] = { 0x118, 2 },
[AI_Mode_2_Register] = { 0x11a, 2 },
struct ni_private *devpriv = dev->private;
/* Make sure we're not using the serial part of the dio */
- if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
+ if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
+ devpriv->serial_interval_ns)
return -EBUSY;
if (comedi_dio_update_state(s, data)) {
- devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
- devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
- ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
+ devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
+ devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
+ ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
}
data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
unsigned int status1;
int err = 0, count = 20;
- devpriv->dio_output &= ~DIO_Serial_Data_Mask;
- devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
- ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
+ devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
+ devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
+ ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
status1 = ni_stc_readw(dev, Joint_Status_1_Register);
if (status1 & DIO_Serial_IO_In_Progress_St) {
/* Output current bit; note that we cannot touch s->state
because it is a per-subdevice field, and serial is
a separate subdevice from DIO. */
- devpriv->dio_output &= ~DIO_SDOUT;
+ devpriv->dio_output &= ~NISTC_DIO_SDOUT;
if (data_out & mask)
- devpriv->dio_output |= DIO_SDOUT;
- ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
+ devpriv->dio_output |= NISTC_DIO_SDOUT;
+ ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
/* Assert SDCLK (active low, inverted), wait for half of
the delay, deassert SDCLK, and wait for the other half. */
udelay((devpriv->serial_interval_ns + 999) / 2000);
/* Input current bit */
- if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN)
+ if (ni_stc_readw(dev, DIO_Parallel_Input_Register) &
+ NISTC_DIO_SDIN)
input |= mask;
}
#define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1)
#define NISTC_AO_CMD1_UPDATE_PULSE BIT(0)
+#define NISTC_DIO_OUT_REG 10
+#define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8)
+#define NISTC_DIO_OUT_SERIAL_MASK NISTC_DIO_OUT_SERIAL(0xff)
+#define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff)
+#define NISTC_DIO_OUT_PARALLEL_MASK NISTC_DIO_OUT_PARALLEL(0xff)
+#define NISTC_DIO_SDIN BIT(4)
+#define NISTC_DIO_SDOUT BIT(0)
+
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
#define DIO_Parallel_Input_Register 7
-#define DIO_Output_Register 10
-#define DIO_Parallel_Data_Out(a) ((a)&0xff)
-#define DIO_Parallel_Data_Mask 0xff
-#define DIO_SDOUT _bit0
-#define DIO_SDIN _bit4
-#define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
-#define DIO_Serial_Data_Mask 0xff00
-
#define DIO_Control_Register 11
#define DIO_Software_Serial_Control _bit11
#define DIO_HW_Serial_Timebase _bit10