signal addr_c_in : std_logic;
signal addr_c : std_logic;
-signal ea_carry_reg_we_n : std_logic;
-signal ea_carry_reg_in : std_logic;
-signal ea_carry_reg : std_logic;
-
signal pcl_carry_reg_in : std_logic;
----------- signals for arithmatic ----------
ah_dff : d_flip_flop generic map (dsize)
port map(clk, '1', '1', ah_buf_we_n, ah_reg_in, ah_reg);
- ea_carry_dff_bit : d_flip_flop_bit
- port map(clk, '1', '1', ea_carry_reg_we_n, ea_carry_reg_in, ea_carry_reg);
-
--pcl carry flag set.
pcl_carry_reg_in <= addr_c when pcl_inc_n = '0' else
'0';
---rel val is on the d_bus.
addr2 <= int_d_bus;
addr_back <= addr_out;
-
- --sustain ea_carry in the register.
- --because looop back bal is changed and it affect the result of
- --EA in the next cycle.
- ea_carry_reg_we_n <= '0';
- ea_carry_reg_in <= addr_c;
- ea_carry <= ea_carry_reg;
+ ea_carry <= addr_c;
--keep the value in the cycle
al_buf_we_n <= '0';
else
al_buf_we_n <= '1';
ah_buf_we_n <= '1';
- ea_carry_reg_we_n <= '1';
abl <= bal;
abh <= bah;
-- page boundary handling
signal a2_abs_xy_next_cycle : std_logic_vector (5 downto 0);
signal a2_indir_y_next_cycle : std_logic_vector (5 downto 0);
+signal a58_branch_next_cycle : std_logic_vector (5 downto 0);
signal wait_a2_abs_xy_next : std_logic;
signal wait_a2_indir_y_next : std_logic;
+signal wait_a58_branch_next : std_logic;
begin
T0;
a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
T0;
+ a58_branch_next_cycle <= T3 when ea_carry = '1' else
+ T0;
- main_p : process (set_clk, res_n, nmi_n, a2_abs_xy_next_cycle, a2_indir_y_next_cycle)
+ main_p : process (set_clk, res_n, nmi_n,
+ a2_abs_xy_next_cycle, a2_indir_y_next_cycle, a58_branch_next_cycle)
-------------------------------------------------------------
-------------------------------------------------------------
wait_a2_abs_xy_next <= '0';
wait_a2_indir_y_next <= '0';
+ wait_a58_branch_next <= '0';
end procedure;
procedure fetch_inst (inc_pcl : in std_logic) is
back_oe(pch_cmd, '0');
back_we(pcl_cmd, '0');
- next_cycle <= T3;
+ wait_a58_branch_next <= '1';
+ next_cycle <= a58_branch_next_cycle;
elsif exec_cycle = T3 then
- if ea_carry = '1' then
- d_print("page crossed.");
- --page crossed. adh calc.
- back_we(pcl_cmd, '1');
- back_oe(pcl_cmd, '0');
- back_oe(pch_cmd, '0');
- back_we(pch_cmd, '0');
- dl_dh_oe_n <= '0';
-
- rel_calc_n <= '0';
- pg_next_n <= not ea_carry;
- next_cycle <= T0;
- else
- --no page boundary.
- --fetch cycle is done.
- t0_cycle;
- end if;
+ d_print("page crossed.");
+ --page crossed. adh calc.
+ back_we(pcl_cmd, '1');
+ back_oe(pcl_cmd, '0');
+ back_oe(pch_cmd, '0');
+ back_we(pch_cmd, '0');
+ dl_dh_oe_n <= '0';
+
+ rel_calc_n <= '0';
+ pg_next_n <= '0';
+ next_cycle <= T0;
end if;
end procedure;
if (a2_indir_y_next_cycle'event) then
if (wait_a2_indir_y_next = '1') then
+ d_print("indir step 2");
next_cycle <= a2_indir_y_next_cycle;
if (ea_carry = '1') then
a2_page_next;
end if;
end if;
+ if (a58_branch_next_cycle'event) then
+ if (wait_a58_branch_next = '1') then
+ d_print("branch step 2");
+ next_cycle <= a58_branch_next_cycle;
+ if (ea_carry = '1') then
+ a2_page_next;
+ end if;
+ end if;
+ end if;
+
if (set_clk'event and set_clk = '1' and res_n = '1') then
d_print(string'("-"));