- conditional branch code changed to update exec cycle

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 486da00..60329c8 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -131,10 +131,6 @@ signal addr_out : std_logic_vector (dsize - 1 downto 0);
 signal addr_c_in : std_logic;
 signal addr_c : std_logic;
 
-signal ea_carry_reg_we_n : std_logic;
-signal ea_carry_reg_in : std_logic;
-signal ea_carry_reg : std_logic;
-
 signal pcl_carry_reg_in : std_logic;
 
 ----------- signals for arithmatic ----------
@@ -169,9 +165,6 @@ begin
     ah_dff : d_flip_flop generic map (dsize) 
             port map(clk, '1', '1', ah_buf_we_n, ah_reg_in, ah_reg);
 
-    ea_carry_dff_bit : d_flip_flop_bit 
-            port map(clk, '1', '1', ea_carry_reg_we_n, ea_carry_reg_in, ea_carry_reg);
-
     --pcl carry flag set.
     pcl_carry_reg_in <= addr_c when pcl_inc_n = '0' else
                 '0';
@@ -403,13 +396,7 @@ end procedure;
             ---rel val is on the d_bus.
             addr2 <= int_d_bus;
             addr_back <= addr_out;
-
-            --sustain ea_carry in the register.
-            --because looop back bal is changed and it affect the result of
-            --EA in the next cycle.
-            ea_carry_reg_we_n <= '0';
-            ea_carry_reg_in <= addr_c;
-            ea_carry <= ea_carry_reg;
+            ea_carry <= addr_c;
 
             --keep the value in the cycle
             al_buf_we_n <= '0';
@@ -496,7 +483,6 @@ end procedure;
     else
         al_buf_we_n <= '1';
         ah_buf_we_n <= '1';
-        ea_carry_reg_we_n <= '1';
 
         abl <= bal;
         abh <= bah;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index c866536..e8a7b57 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -156,8 +156,10 @@ signal nmi_handled_n : std_logic;
 -- page boundary handling
 signal a2_abs_xy_next_cycle     : std_logic_vector (5 downto 0);
 signal a2_indir_y_next_cycle    : std_logic_vector (5 downto 0);
+signal a58_branch_next_cycle    : std_logic_vector (5 downto 0);
 signal wait_a2_abs_xy_next      : std_logic;
 signal wait_a2_indir_y_next     : std_logic;
+signal wait_a58_branch_next     : std_logic;
 
 begin
 
@@ -170,8 +172,11 @@ begin
                     T0;
     a2_indir_y_next_cycle <= T5 when ea_carry = '1' else
                     T0;
+    a58_branch_next_cycle <= T3 when ea_carry = '1' else
+                    T0;
 
-    main_p : process (set_clk, res_n, nmi_n, a2_abs_xy_next_cycle, a2_indir_y_next_cycle)
+    main_p : process (set_clk, res_n, nmi_n, 
+                     a2_abs_xy_next_cycle, a2_indir_y_next_cycle, a58_branch_next_cycle)
 
 -------------------------------------------------------------
 -------------------------------------------------------------
@@ -268,6 +273,7 @@ begin
 
     wait_a2_abs_xy_next <= '0';
     wait_a2_indir_y_next <= '0';
+    wait_a58_branch_next <= '0';
 end  procedure;
 
 procedure fetch_inst (inc_pcl : in std_logic) is
@@ -945,25 +951,20 @@ begin
         back_oe(pch_cmd, '0');
         back_we(pcl_cmd, '0');
 
-        next_cycle <= T3;
+        wait_a58_branch_next <= '1';
+        next_cycle <= a58_branch_next_cycle;
     elsif exec_cycle = T3 then
-        if ea_carry = '1' then
-            d_print("page crossed.");
-            --page crossed. adh calc.
-            back_we(pcl_cmd, '1');
-            back_oe(pcl_cmd, '0');
-            back_oe(pch_cmd, '0');
-            back_we(pch_cmd, '0');
-            dl_dh_oe_n <= '0';
-
-            rel_calc_n <= '0';
-            pg_next_n <= not ea_carry;
-            next_cycle <= T0;
-        else
-            --no page boundary. 
-            --fetch cycle is done.
-            t0_cycle;
-        end if;
+        d_print("page crossed.");
+        --page crossed. adh calc.
+        back_we(pcl_cmd, '1');
+        back_oe(pcl_cmd, '0');
+        back_oe(pch_cmd, '0');
+        back_we(pch_cmd, '0');
+        dl_dh_oe_n <= '0';
+
+        rel_calc_n <= '0';
+        pg_next_n <= '0';
+        next_cycle <= T0;
     end if;
 end  procedure;
 
@@ -1002,6 +1003,7 @@ end  procedure;
 
         if (a2_indir_y_next_cycle'event) then
             if (wait_a2_indir_y_next = '1') then
+                d_print("indir step 2");
                 next_cycle <= a2_indir_y_next_cycle;
                 if (ea_carry = '1') then
                     a2_page_next;
@@ -1009,6 +1011,16 @@ end  procedure;
             end if;
         end if;
 
+        if (a58_branch_next_cycle'event) then
+            if (wait_a58_branch_next = '1') then
+                d_print("branch step 2");
+                next_cycle <= a58_branch_next_cycle;
+                if (ea_carry = '1') then
+                    a2_page_next;
+                end if;
+            end if;
+        end if;
+
         if (set_clk'event and set_clk = '1' and res_n = '1') then
             d_print(string'("-"));
 

diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 137c333..20f35a6 100644 (file)
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -611,13 +611,6 @@ boundary_3_4:
     ;;branch page cross test.\r
     jmp bl_test0\r
 \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
 bl_test0:\r
     ldx #5\r
 bl_test1:\r