addressing refactoring...

diff --git a/de1_nes/cpu/decoder.vhd b/de1_nes/cpu/decoder.vhd
index 7d57f47..4abd559 100644 (file)
--- a/de1_nes/cpu/decoder.vhd
+++ b/de1_nes/cpu/decoder.vhd
@@ -92,9 +92,6 @@ constant T4 : std_logic_vector (5 downto 0) := "000100";
 constant T5 : std_logic_vector (5 downto 0) := "000101";
 constant T6 : std_logic_vector (5 downto 0) := "000110";
 
---T0r (T0 after reset) is the special cycle for very beginning T0 cycle of reset/nmi/irq.
-constant T0r : std_logic_vector (5 downto 0) := "000111";
-
 --01xxx : reset cycle : R0 > R1 > R2 > R3 > R4 > R5 > T0
 constant R0 : std_logic_vector (5 downto 0) := "001000";
 constant R1 : std_logic_vector (5 downto 0) := "001001";
@@ -221,6 +218,7 @@ begin
     back_oe(pcl_cmd, '1');
     back_oe(pch_cmd, '1');
     back_we(pcl_cmd, '1');
+    ad_oe_n <= '1';
 end procedure;
 
 procedure read_status is
@@ -278,7 +276,7 @@ begin
 
 end  procedure;
 
-procedure fetch_inst (wk_inc_pcl_n : in std_logic) is
+procedure fetch_inst is
 begin
     if instruction = conv_std_logic_vector(16#4c#, dsize) then
         --if prior cycle is jump instruction, 
@@ -296,8 +294,7 @@ begin
     ad_oe_n <= '0';
     pch_cmd <= "1101";
     inst_we_n <= '0';
-    pcl_inc_n <= wk_inc_pcl_n;
-    ba_out_n <= not wk_inc_pcl_n;
+    pcl_inc_n <= '0';
     r_nw <= '1';
 
     d_print(string'("fetch 1"));
@@ -306,15 +303,16 @@ end  procedure;
 ---T0 cycle routine 
 ---(along with the page boundary condition, the last 
 ---cycle is bypassed and slided to T0.)
-procedure t0_cycle(wk_inc_pcl_n : in std_logic) is
+procedure t0_cycle is
 begin
     disable_pins;
     if (nmi_n = '0' and nmi_handled_n = '1') then
         --start nmi handling...
-        fetch_inst('1');
+        --fetch_inst('1');
         wk_next_cycle <= N1;
     else
-        fetch_inst(wk_inc_pcl_n);
+        fetch_inst;
+        ba_out_n <= '1';
         wk_next_cycle <= T1;
     end if;
 end  procedure;
@@ -1119,13 +1117,9 @@ end  procedure;
                 r_nw <= 'Z';
                 ba_out_n <= '1';
 
-            elsif (exec_cycle = T0r) then
-                --cycle #1
-                t0_cycle('1');
-
             elsif (exec_cycle = T0 and ea_carry = '0') then
                 --cycle #1
-                t0_cycle('0');
+                t0_cycle;
 
             elsif exec_cycle = T1 or exec_cycle = T2 or exec_cycle = T3 or 
                 exec_cycle = T4 or exec_cycle = T5 or exec_cycle = T6 or 
@@ -2872,7 +2866,7 @@ end  procedure;
                     nmi_handled_n <= '0';
                 end if;
                 --start execute cycle.
-                wk_next_cycle <= T0r;
+                wk_next_cycle <= T0;
 
             end if; --if rdy = '0' then
 

diff --git a/de1_nes/cpu/mos6502.vhd b/de1_nes/cpu/mos6502.vhd
index 8c27a7c..460717a 100644 (file)
--- a/de1_nes/cpu/mos6502.vhd
+++ b/de1_nes/cpu/mos6502.vhd
@@ -519,9 +519,9 @@ begin
             port map(dbg_sp, set_clk, rst_n, '1', sp_cmd, int_d_bus, addr_back, bal);
 
     x : dual_dff generic map (dsize) 
-            port map(dbg_x, trigger_clk, rst_n, '1', x_cmd, int_d_bus, null_bus, index_bus);
+            port map(dbg_x, set_clk, rst_n, '1', x_cmd, int_d_bus, null_bus, index_bus);
     y : dual_dff generic map (dsize) 
-            port map(dbg_y, trigger_clk, rst_n, '1', y_cmd, int_d_bus, null_bus, index_bus);
+            port map(dbg_y, set_clk, rst_n, '1', y_cmd, int_d_bus, null_bus, index_bus);
 
     acc : dual_dff generic map (dsize) 
             port map(dbg_acc, trigger_clk, rst_n, '1', acc_cmd, int_d_bus, acc_in, acc_out);

diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd
index 66b1176..96bfc78 100644 (file)
--- a/de1_nes/de1_nes.vhd
+++ b/de1_nes/de1_nes.vhd
@@ -32,7 +32,7 @@ entity de1_nes is
 
 --ppu debug pins
     signal dbg_ppu_ce_n    : out std_logic;
-    signal dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
+    signal dbg_ppu_ctrl, dbg_ppu_ctrl_dummy, dbg_ppu_mask, dbg_ppu_status : out std_logic_vector (7 downto 0);
     signal dbg_ppu_addr : out std_logic_vector (13 downto 0);
     signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
     signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
@@ -355,7 +355,7 @@ begin
     --nes ppu instance
     ppu_inst: ppu port map (  
         dbg_ppu_ce_n                                        ,
-        dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status          ,
+        dbg_ppu_ctrl_dummy, dbg_ppu_mask, dbg_ppu_status          ,
         dbg_ppu_addr                                        ,
         dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy        ,
 
@@ -472,7 +472,7 @@ begin
     dbg_nmi <= nmi_n;\r
 \r
     nmi_n <= dummy_nmi;\r
---    dbg_ppu_ctrl <= dbg_pcl;\r
+    dbg_ppu_ctrl <= dbg_pcl;\r
 --    dbg_ppu_mask <= dbg_pch;\r
 --    dbg_ppu_scrl_x(5) <= rom_ce_n;\r
 --    dbg_ppu_scrl_x(6) <= ram_ce_n;\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index 11a6fd4..b9ef00f 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -38,6 +38,7 @@ add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/dbg_e
 add wave -label ea_carry   -radix decimal -unsigned  sim:/testbench_motones_sim/sim_board/dbg_ea_carry     \r
 #add wave -label wait_a58_branch_next -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next     \r
 \r
+add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
 \r
 \r
 #add wave -divider regs\r
@@ -117,7 +118,7 @@ wave zoom full
 \r
 #wave zoom range 3339700 ps 5138320 ps\r
 \r
-run 30 us\r
+run 5 us\r
 \r
 ##wave addcursor 907923400 ps\r
 \r