drm/i915: add DP support to intel_ddi_pll_mode_set

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e58df71..5071370 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -763,6 +763,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 {
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+       struct drm_encoder *encoder = &intel_encoder->base;
        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
        struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
        int type = intel_encoder->type;
@@ -773,7 +774,29 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 
        intel_ddi_put_crtc_pll(crtc);
 
-       if (type == INTEL_OUTPUT_HDMI) {
+       if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+               switch (intel_dp->link_bw) {
+               case DP_LINK_BW_1_62:
+                       intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+                       break;
+               case DP_LINK_BW_2_7:
+                       intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+                       break;
+               case DP_LINK_BW_5_4:
+                       intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+                       break;
+               default:
+                       DRM_ERROR("Link bandwidth %d unsupported\n",
+                                 intel_dp->link_bw);
+                       return false;
+               }
+
+               /* We don't need to turn any PLL on because we'll use LCPLL. */
+               return true;
+
+       } else if (type == INTEL_OUTPUT_HDMI) {
                int p, n2, r2;
 
                if (plls->wrpll1_refcount == 0) {