val = s->b;
break;
case VIA_REG_A:
+ qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
+ /* fall through */
+ case VIA_REG_ANH:
val = s->a;
break;
case VIA_REG_DIRB:
val = s->ier | 0x80;
break;
default:
- case VIA_REG_ANH:
- val = s->anh;
- break;
+ g_assert_not_reached();
}
if (addr != VIA_REG_IFR || val != 0) {
mdc->portB_write(s);
break;
case VIA_REG_A:
+ qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
+ /* fall through */
+ case VIA_REG_ANH:
s->a = (s->a & ~s->dira) | (val & s->dira);
mdc->portA_write(s);
break;
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
default:
- case VIA_REG_ANH:
- s->anh = val;
- break;
+ g_assert_not_reached();
}
}
VMSTATE_UINT8(pcr, MOS6522State),
VMSTATE_UINT8(ifr, MOS6522State),
VMSTATE_UINT8(ier, MOS6522State),
- VMSTATE_UINT8(anh, MOS6522State),
VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
vmstate_mos6522_timer, MOS6522Timer),
VMSTATE_END_OF_LIST()
s->ifr = 0;
s->ier = 0;
/* s->ier = T1_INT | SR_INT; */
- s->anh = 0;
s->timers[0].frequency = s->frequency;
s->timers[0].latch = 0xffff;