crypto: caam - fix MC firmware detection

Management Complex (MC) f/w detection is based on CTPR_MS[DPAA2] bit.

This is incorrect since:
-the bit is set for all CAAM blocks integrated in SoCs with a certain
Layerscape Chassis
-some SoCs with LS Chassis don't have an MC block (thus no MC f/w)

To fix this, MC f/w detection will be based on the presence of
"fsl,qoriq-mc" compatible string in the device tree.

Fixes: 297b9cebd2fc0 ("crypto: caam/jr - add support for DPAA2 parts")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index a28868d..538c01f 100644 (file)
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -322,9 +322,9 @@ static int caam_remove(struct platform_device *pdev)
 
        /*
         * De-initialize RNG state handles initialized by this driver.
-        * In case of DPAA 2.x, RNG is managed by MC firmware.
+        * In case of SoCs with Management Complex, RNG is managed by MC f/w.
         */
-       if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)
+       if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init)
                deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 
        /* Shut down debug views */
@@ -618,11 +618,15 @@ static int caam_probe(struct platform_device *pdev)
        /*
         * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
         * long pointers in master configuration register.
-        * In case of DPAA 2.x, Management Complex firmware performs
+        * In case of SoCs with Management Complex, MC f/w performs
         * the configuration.
         */
        caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
-       if (!caam_dpaa2)
+       np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
+       ctrlpriv->mc_en = !!np;
+       of_node_put(np);
+
+       if (!ctrlpriv->mc_en)
                clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
                              MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
                              MCFGR_WDENABLE | MCFGR_LARGE_BURST |
@@ -733,9 +737,9 @@ static int caam_probe(struct platform_device *pdev)
        /*
         * If SEC has RNG version >= 4 and RNG state handle has not been
         * already instantiated, do RNG instantiation
-        * In case of DPAA 2.x, RNG is managed by MC firmware.
+        * In case of SoCs with Management Complex, RNG is managed by MC f/w.
         */
-       if (!caam_dpaa2 &&
+       if (!ctrlpriv->mc_en &&
            (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
                ctrlpriv->rng4_sh_init =
                        rd_reg32(&ctrl->r4tst[0].rdsta);
@@ -804,9 +808,8 @@ static int caam_probe(struct platform_device *pdev)
        /* Report "alive" for developer to see */
        dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
                 ctrlpriv->era);
-       dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
-                ctrlpriv->total_jobrs, ctrlpriv->qi_present,
-                caam_dpaa2 ? "yes" : "no");
+       dev_info(dev, "job rings = %d, qi = %d\n",
+                ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 
 #ifdef CONFIG_DEBUG_FS
        debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,

diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 7696a77..babc78a 100644 (file)
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -82,6 +82,7 @@ struct caam_drv_private {
         */
        u8 total_jobrs;         /* Total Job Rings in device */
        u8 qi_present;          /* Nonzero if QI present in device */
+       u8 mc_en;               /* Nonzero if MC f/w is active */
        int secvio_irq;         /* Security violation interrupt number */
        int virt_en;            /* Virtualization enabled in CAAM */
        int era;                /* CAAM Era (internal HW revision) */