static int readOperands(struct InternalInstruction* insn) {
int index;
int hasVVVV, needVVVV;
+ int sawRegImm = 0;
dbgprintf(insn, "readOperands()");
dbgprintf(insn, "We currently don't hande code-offset encodings");
return -1;
case ENCODING_IB:
+ if (sawRegImm) {
+ // saw a register immediate so don't read again and instead split the previous immediate
+ // FIXME: This is a hack
+ insn->immediates[insn->numImmediatesConsumed++] = insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
+ break;
+ }
if (readImmediate(insn, 1))
return -1;
if (insn->spec->operands[index].type == TYPE_IMM3 &&
insn->immediates[insn->numImmediatesConsumed - 1] > 7)
return -1;
+ if (insn->spec->operands[index].type == TYPE_XMM128 ||
+ insn->spec->operands[index].type == TYPE_XMM256)
+ sawRegImm = 1;
break;
case ENCODING_IW:
if (readImmediate(insn, 2))
[]>;
}
-let isAsmParserOnly = 1 in {
- defm VPERMIL2PD : xop5op<0x49, "vpermil2pd">;
- defm VPERMIL2PS : xop5op<0x48, "vpermil2ps">;
-}
+defm VPERMIL2PD : xop5op<0x49, "vpermil2pd">;
+defm VPERMIL2PS : xop5op<0x48, "vpermil2ps">;
# CHECK: vfmadd132sd (%rax), %xmm12, %xmm10
0xc4 0x62 0x99 0x99 0x10
-# CHEDCK: vfmaddss (%rcx), %xmm1, %xmm0, %xmm0
+# CHECK: vfmaddss (%rcx), %xmm1, %xmm0, %xmm0
0xc4 0xe3 0xf9 0x6a 0x01 0x10
-# CHEDCK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0
+# CHECK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0
0xc4 0xe3 0x79 0x6a 0x01 0x10
+
+# CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0
+0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21
bool hasFROperands = false;
- assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
+ assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
if (OperandList[operandIndex].Constraints.size()) {
// Operand 3 (optional) is an immediate.
if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
- assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
+ assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
"Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
else
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
if (HasVEX_4VOp3Prefix)
HANDLE_OPERAND(vvvvRegister)
- HANDLE_OPTIONAL(immediate)
+ if (!HasMemOp4Prefix)
+ HANDLE_OPTIONAL(immediate)
+ HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
break;
case X86Local::MRMSrcMem:
// Operand 1 is a register operand in the Reg/Opcode field.
// Operand 3 (optional) is an immediate.
if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
- assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
+ assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
"Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
else
assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
if (HasVEX_4VOp3Prefix)
HANDLE_OPERAND(vvvvRegister)
- HANDLE_OPTIONAL(immediate)
+ if (!HasMemOp4Prefix)
+ HANDLE_OPTIONAL(immediate)
+ HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
break;
case X86Local::MRM0r:
case X86Local::MRM1r: