--attribute ram_init_file : string;
--attribute ram_init_file of p_rom : signal is "sample1-prg.hex";
+signal wk_data : std_logic_vector (dbus_size - 1 downto 0);
+
begin
p : process (clk)
begin
if (rising_edge(clk)) then
if (ce_n = '0') then
- data <= p_rom(conv_integer(addr));
+ wk_data <= p_rom(conv_integer(addr));
else
- data <= (others => 'Z');
+ wk_data <= (others => 'Z');
end if;
end if;
end process;
+
+ data <= wk_data when ce_n = '0' else
+ (others => 'Z');
end rtl;
constant RAM_TAOE : time := 25 ns; --OE access time
constant RAM_TOH : time := 10 ns; --write data hold time
+signal wk_d_io : std_logic_vector (dbus_size - 1 downto 0);
+
begin
p_write : process (clk)
begin
begin
if (rising_edge(clk)) then
if (ce_n= '0' and we_n = '1' and oe_n = '0') then
- d_io <= work_ram(conv_integer(addr));
+ wk_d_io <= work_ram(conv_integer(addr));
else
- d_io <= (others => 'Z');
+ wk_d_io <= (others => 'Z');
end if;
end if;
end process;
+
+ d_io <= wk_d_io when ce_n= '0' and we_n = '1' and oe_n = '0' else
+ (others => 'Z');
end rtl;
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