a2 inst all addressing supported.

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index a274ac2..cba05c8 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -473,7 +473,12 @@ begin
                 end if;\r
             when ST_A25_T3 =>\r
                 if (reg_sub_state = ST_SUB73) then\r
-                    reg_main_next_state <= ST_A25_T4;\r
+                    --abs xy move to next only when page crossed.\r
+                    if (reg_tmp_pg_crossed = '1') then\r
+                        reg_main_next_state <= ST_A25_T4;\r
+                    else\r
+                        reg_main_next_state <= ST_CM_T0;\r
+                    end if;\r
                 else\r
                     reg_main_next_state <= reg_main_state;\r
                 end if;\r
@@ -521,7 +526,12 @@ begin
                 end if;\r
             when ST_A27_T4 =>\r
                 if (reg_sub_state = ST_SUB73) then\r
-                    reg_main_next_state <= ST_A27_T5;\r
+                    --indir, y move to next only when page crossed.\r
+                    if (reg_tmp_pg_crossed = '1') then\r
+                        reg_main_next_state <= ST_A27_T5;\r
+                    else\r
+                        reg_main_next_state <= ST_CM_T0;\r
+                    end if;\r
                 else\r
                     reg_main_next_state <= reg_main_state;\r
                 end if;\r
@@ -1117,33 +1127,57 @@ end;
                     pc_inc;\r
                 end if;\r
 \r
-           --a3 instructions.\r
-           --sta, stx, sty\r
-            elsif (reg_main_state = ST_A33_T2 or\r
-                reg_main_state = ST_A35_T2\r
+            --intermediate cycles..\r
+            elsif (reg_main_state = ST_A24_T2 or\r
+                reg_main_state = ST_A26_T2 or\r
+                reg_main_state = ST_A33_T2 or\r
+                reg_main_state = ST_A35_T2 or\r
+                reg_main_state = ST_A27_T2 or\r
+                reg_main_state = ST_A36_T2\r
                 ) then\r
                 --zp xy\r
                 --ind, x\r
-                --discarded cycle.\r
+                -->>discarded cycle.\r
+                --ind, y\r
+                --ial cycle.\r
                 reg_addr    <= "00000000" & reg_idl_l;\r
                 reg_d_out   <= (others => 'Z');\r
                 reg_r_nw    <= '1';\r
-            elsif (reg_main_state = ST_A33_T3) then\r
+            elsif (reg_main_state = ST_A24_T3 or\r
+                reg_main_state = ST_A33_T3) then\r
                 --ind, x\r
                 --bal + x cycle.\r
-                reg_addr    <= "00000000" & reg_idl_l;\r
+                reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
                 reg_d_out   <= (others => 'Z');\r
                 reg_r_nw    <= '1';\r
-            elsif (reg_main_state = ST_A33_T4) then\r
+            elsif (reg_main_state = ST_A24_T4 or\r
+                reg_main_state = ST_A33_T4) then\r
                 --ind, x\r
                 --bal + x + 1 cycle.\r
-                reg_addr    <= "00000000" & (reg_idl_l + 1);\r
+                reg_addr    <= "00000000" & (reg_idl_l + reg_x + 1);\r
                 reg_d_out   <= (others => 'Z');\r
                 reg_r_nw    <= '1';\r
-            elsif (reg_main_state = ST_A34_T3) then\r
+            elsif (reg_main_state = ST_A25_T3 or\r
+                reg_main_state = ST_A34_T3) then\r
                 --abs xy\r
-                --discarded cycle.\r
-                if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
+                --(discarded cycle for store inst..)\r
+                if (reg_inst(1 downto 0) = "01") then\r
+                    if (reg_inst(4 downto 2) = "110") then\r
+                        --abs y\r
+                        reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
+                    elsif (reg_inst(4 downto 2) = "111") then\r
+                        --abs x\r
+                        reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
+                    end if; \r
+                elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
+                    --abs y\r
+                    --ldx\r
+                    reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
+                elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
+                    --abs x\r
+                    --ldy\r
+                    reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
+                elsif (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
                     --sta, x\r
                     reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
                     calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
@@ -1156,19 +1190,15 @@ end;
                 reg_r_nw    <= '1';\r
 \r
                 reg_tmp_pg_crossed <= calc_adl(8);\r
-            elsif (reg_main_state = ST_A36_T2) then\r
-                --ind, y\r
-                --ial cycle.\r
-                reg_addr    <= "00000000" & reg_idl_l;\r
-                reg_d_out   <= (others => 'Z');\r
-                reg_r_nw    <= '1';\r
-            elsif (reg_main_state = ST_A36_T3) then\r
+            elsif (reg_main_state = ST_A27_T3 or\r
+                reg_main_state = ST_A36_T3) then\r
                 --ind, y\r
                 --ial + 1 cycle.\r
                 reg_addr    <= "00000000" & (reg_idl_l + 1);\r
                 reg_d_out   <= (others => 'Z');\r
                 reg_r_nw    <= '1';\r
-            elsif (reg_main_state = ST_A36_T4) then\r
+            elsif (reg_main_state = ST_A27_T4 or\r
+                reg_main_state = ST_A36_T4) then\r
                 --ind, y\r
                 --bal + y cycle.\r
                 reg_addr    <= reg_tmp_h & (reg_tmp_l + reg_y);\r
@@ -1177,6 +1207,76 @@ end;
                 calc_adl    := ("0" & reg_tmp_l) + ("0" & reg_y);\r
                 reg_tmp_pg_crossed <= calc_adl(8);\r
 \r
+\r
+           --a2 instructions.\r
+            elsif (reg_main_state = ST_A22_T2 or\r
+                reg_main_state = ST_A23_T3 or\r
+                reg_main_state = ST_A24_T5 or\r
+                reg_main_state = ST_A25_T4 or\r
+                reg_main_state = ST_A26_T3 or\r
+                reg_main_state = ST_A27_T5\r
+            ) then\r
+                --execute cycle.\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+\r
+                --address bus out.\r
+                if (reg_main_state = ST_A22_T2) then\r
+                    --zp\r
+                    reg_addr    <= "00000000" & reg_idl_l;\r
+\r
+                elsif (reg_main_state = ST_A23_T3) then\r
+                    --abs\r
+                    reg_addr    <= reg_idl_h & reg_idl_l;\r
+\r
+                elsif (reg_main_state = ST_A24_T5) then\r
+                    --ind, x\r
+                    reg_addr    <= reg_tmp_h & reg_tmp_l;\r
+\r
+                elsif (reg_main_state = ST_A25_T4) then\r
+                    --abs xy\r
+                    if (reg_inst(1 downto 0) = "01") then\r
+                        if (reg_inst(4 downto 2) = "110") then\r
+                            --abs y\r
+                            reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+                        elsif (reg_inst(4 downto 2) = "111") then\r
+                            --abs x\r
+                            reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+                        end if; \r
+                    elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
+                        --abs y\r
+                        --ldx\r
+                        reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+                    elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
+                        --abs x\r
+                        --ldy\r
+                        reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+                    end if; \r
+\r
+                elsif (reg_main_state = ST_A26_T3) then\r
+                    --zp xy\r
+                    if (reg_inst(1 downto 0) = "01") then\r
+                        if (reg_inst(4 downto 2) = "101") then\r
+                            --zp x\r
+                            reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
+                        end if; \r
+                    elsif (reg_inst = conv_std_logic_vector(16#b6#, 8)) then\r
+                        --zp y\r
+                        --ldx\r
+                        reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
+                    elsif (reg_inst = conv_std_logic_vector(16#b4#, 8)) then\r
+                        --zp y\r
+                        --ldy\r
+                        reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
+                    end if; \r
+\r
+                elsif (reg_main_state = ST_A27_T5) then\r
+                    --ind y\r
+                    reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
+                end if;\r
+\r
+           --a3 instructions.\r
+           --sta, stx, sty\r
             elsif (reg_main_state = ST_A31_T2 or\r
                 reg_main_state = ST_A32_T3 or\r
                 reg_main_state = ST_A33_T5 or\r