ppu address decoder added.

diff --git a/simulation/address_decoder.vhd b/simulation/address_decoder.vhd
index ec2ffea..4c0ba0c 100644 (file)
--- a/simulation/address_decoder.vhd
+++ b/simulation/address_decoder.vhd
@@ -126,9 +126,11 @@ use ieee.std_logic_1164.all;
 entity v_address_decoder is
 generic (abus_size : integer := 14; dbus_size : integer := 8);
     port (  clk         : in std_logic; 
-            R_nW        : in std_logic;
-            v_addr      : in std_logic_vector (abus_size - 1 downto 0);
-            v_io        : inout std_logic_vector (dbus_size - 1 downto 0)
+            rd_n        : in std_logic;
+            wr_n        : in std_logic;
+            ale         : in std_logic;
+            vram_ad     : inout std_logic_vector (7 downto 0);
+            vram_a      : in std_logic_vector (13 downto 8)
         );
 end v_address_decoder;
 
@@ -161,43 +163,62 @@ architecture rtl of v_address_decoder is
         );
     end component;
 
+    component ls373
+        generic (
+            dsize : integer := 8
+        );
+        port (  c         : in std_logic;
+                oc_n      : in std_logic;
+                d         : in std_logic_vector(dsize - 1 downto 0);
+                q         : out std_logic_vector(dsize - 1 downto 0)
+        );
+    end component;
+
     constant dsize : integer := 8;
     constant vram_1k : integer := 10;      --2k = 11 bit width.
     constant chr_rom_8k : integer := 13;     --32k = 15 bit width.
 
+
+    signal v_addr : std_logic_vector (13 downto 0);
     signal oe_n : std_logic;
+    --signal nt_v_mirror2  : std_logic;
     signal nt_v_mirror  : std_logic;
 
     signal pt_ce_n : std_logic;
     signal nt0_ce_n : std_logic;
     signal nt1_ce_n : std_logic;
     signal plt_ce_n : std_logic;
+
 begin
 
-    oe_n <= not R_nW;
+    --transparent d-latch
+    latch_inst : ls373 generic map (dsize)
+                port map(ale, '0', vram_ad, v_addr(7 downto 0));
+    v_addr (13 downto 8) <= vram_a;
 
     --pattern table
-    pt_ce_n <= '0' when (v_addr(13) = '0' and R_nW = '1') else
+    pt_ce_n <= '0' when (v_addr(13) = '0' and rd_n = '0') else
              '1' ;
+    --nt_v_mirror <= '0';
     pattern_tbl : chr_rom generic map (chr_rom_8k, dsize)
-            port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), v_io, nt_v_mirror);
+            port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
 
     --name table/attr table
     name_tbl0 : ram generic map (vram_1k, dsize)
-            port map (nt0_ce_n, oe_n, R_nW, 
-                    v_addr(vram_1k - 1 downto 0), v_io);
+            port map (nt0_ce_n, rd_n, wr_n, 
+                    v_addr(vram_1k - 1 downto 0), vram_ad);
 
     name_tbl1 : ram generic map (vram_1k, dsize)
-            port map (nt1_ce_n, oe_n, R_nW, 
-                    v_addr(vram_1k - 1 downto 0), v_io);
+            port map (nt1_ce_n, rd_n, wr_n, 
+                    v_addr(vram_1k - 1 downto 0), vram_ad);
 
     --palette table
     plt_tbl : ram generic map (4, dsize)
-            port map (plt_ce_n, oe_n, R_nW, 
-                    v_addr(3 downto 0), v_io);
+            port map (plt_ce_n, rd_n, wr_n, 
+                    v_addr(3 downto 0), vram_ad);
 
     --ram io timing.
-    main_p : process (clk, v_addr, v_io, R_nW)
+    main_p : process (clk, v_addr, vram_ad, wr_n)
     begin
         if (v_addr(13) = '1') then
             ---name tbl
@@ -208,10 +229,10 @@ begin
                     if (v_addr(10) = '0') then
                         --name table 0 enable.
                         nt1_ce_n <= '1';
-                        if (R_nW = '0') then
+                        if (wr_n = '0') then
                             --write
                             nt0_ce_n <= not clk;
-                        elsif (R_nW = '1') then 
+                        elsif (rd_n = '0') then 
                             --read
                             nt0_ce_n <= '0';
                         else
@@ -220,10 +241,10 @@ begin
                     else
                         --name table 1 enable.
                         nt0_ce_n <= '1';
-                        if (R_nW = '0') then
+                        if (wr_n = '0') then
                             --write
                             nt1_ce_n <= not clk;
-                        elsif (R_nW = '1') then 
+                        elsif (rd_n = '0') then 
                             --read
                             nt1_ce_n <= '0';
                         else
@@ -236,10 +257,10 @@ begin
                     if (v_addr(11) = '0') then
                         --name table 0 enable.
                         nt1_ce_n <= '1';
-                        if (R_nW = '0') then
+                        if (wr_n = '0') then
                             --write
                             nt0_ce_n <= not clk;
-                        elsif (R_nW = '1') then 
+                        elsif (rd_n = '0') then 
                             --read
                             nt0_ce_n <= '0';
                         else
@@ -248,10 +269,10 @@ begin
                     else
                         --name table 1 enable.
                         nt0_ce_n <= '1';
-                        if (R_nW = '0') then
+                        if (wr_n = '0') then
                             --write
                             nt1_ce_n <= not clk;
-                        elsif (R_nW = '1') then 
+                        elsif (rd_n = '0') then 
                             --read
                             nt1_ce_n <= '0';
                         else
@@ -266,10 +287,10 @@ begin
 
             ---palette table
             if (v_addr(12 downto 8) = "11111") then
-                if (R_nW = '0') then
+                if (wr_n = '0') then
                     --write
                     plt_ce_n <= not clk;
-                elsif (R_nW = '1') then 
+                elsif (rd_n = '0') then 
                     --read
                     plt_ce_n <= '0';
                 else

diff --git a/simulation/testbench_address_decoder.vhd b/simulation/testbench_address_decoder.vhd
index 474074f..200ebbd 100644 (file)
--- a/simulation/testbench_address_decoder.vhd
+++ b/simulation/testbench_address_decoder.vhd
@@ -22,12 +22,28 @@ architecture stimulus of testbench_address_decoder is
     component v_address_decoder
     generic (abus_size : integer := 14; dbus_size : integer := 8);
         port (  clk         : in std_logic; 
-                R_nW        : in std_logic;
-                v_addr      : in std_logic_vector (abus_size - 1 downto 0);
-                v_io        : inout std_logic_vector (dbus_size - 1 downto 0)
+                rd_n        : in std_logic;
+                wr_n        : in std_logic;
+                ale         : in std_logic;
+                vram_ad     : inout std_logic_vector (7 downto 0);
+                vram_a      : in std_logic_vector (13 downto 8)
             );
     end component;
 
+component d_flip_flop
+    generic (
+            dsize : integer := 8
+            );
+    port (  
+            clk     : in std_logic;
+            res_n   : in std_logic;
+            set_n   : in std_logic;
+            we_n    : in std_logic;
+            d       : in std_logic_vector (dsize - 1 downto 0);
+            q       : out std_logic_vector (dsize - 1 downto 0)
+        );
+end component;
+
     constant cpu_clk : time := 589 ns;
     constant size8 : integer := 8;
     constant size16 : integer := 16;
@@ -39,9 +55,16 @@ architecture stimulus of testbench_address_decoder is
     signal aa16         : std_logic_vector (size16 - 1 downto 0);
     signal dd8_io       : std_logic_vector (size8 - 1 downto 0);
 
-    signal v_r_nw       : std_logic;
+    signal v_ad         : std_logic_vector (size8 - 1 downto 0);
+    signal v_a          : std_logic_vector (size14 - 1 downto size8);
     signal v_addr       : std_logic_vector (size14 - 1 downto 0);
-    signal v_io         : std_logic_vector (size8 - 1 downto 0);
+    signal v_data       : std_logic_vector (size8 - 1 downto 0);
+
+    signal v_rd_n       : std_logic;
+    signal v_wr_n       : std_logic;
+    signal v_ale        : std_logic;
+
+    signal v_dff_we_n        : std_logic;
 
 begin
     dut0 : address_decoder generic map (size16, size8) 
@@ -316,8 +339,14 @@ begin
         wait;
     end process;
 
+    v_ad <= v_addr(size8 - 1 downto 0);
+    v_a <= v_addr(size14 - 1 downto size8);
+
     dut1 : v_address_decoder generic map (size14, size8) 
-        port map (phi2, v_r_nw, v_addr, v_io);
+        port map (phi2, v_rd_n, v_wr_n, v_ale, v_ad, v_a);
+
+    dff : d_flip_flop generic map (size8)
+        port map (cclk, '1', '1', v_dff_we_n, v_ad, v_data);
 
     -----test for vram/chr-rom
     p3 : process
@@ -329,116 +358,139 @@ begin
         --syncronize with clock dropping edge.
         wait for cpu_clk / 2;
 
-        ---read test.
-        v_io <= (others => 'Z');
-        v_r_nw <= '1';
-
-        --pattern tbl
-        v_addr <= conv_std_logic_vector(0, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#0001#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#0005#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#1f00#, size14);
-        wait for cpu_clk;
-
-        --name tbl
-        v_addr <= conv_std_logic_vector(16#2000#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#2100#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#2400#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#2800#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#2c00#, size14);
-        wait for cpu_clk;
-
-        --palette tbl
-        v_addr <= conv_std_logic_vector(16#3f00#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#3fff#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#33ff0#, size14);
-        wait for cpu_clk;
-
-        v_addr <= conv_std_logic_vector(16#3ff5#, size14);
-        wait for cpu_clk;
-
-        ----all data, selctor check.
-        for i in 0 to 16#4000# - 1 loop
-            --read rom
-            v_addr <= conv_std_logic_vector(16#0000# + i, size14);
-            wait for cpu_clk;
-        end loop;
 
         --copy from chr rom to name tbl.
         for i in 0 to loopcnt loop
             --read rom
-            v_r_nw <= '1';
-            v_io <= (others => 'Z');
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_wr_n <= '1';
+            v_dff_we_n <= '1';
             v_addr <= conv_std_logic_vector(16#0000# + i, size14);
             wait for cpu_clk;
+            v_dff_we_n <= '0';
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
+            v_wr_n <= '1';
+            wait for cpu_clk;
 
             --write name tbl #0
+            v_dff_we_n <= '1';
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_wr_n <= '1';
             v_addr <= conv_std_logic_vector(16#2000# + i, size14);
-            v_io <= v_io;
-            v_r_nw <= '0';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '1';
+            v_wr_n <= '0';
+            v_addr(7 downto 0) <= v_data;
             wait for cpu_clk;
         end loop;
 
         --data check...
+        v_wr_n <= '1';
         for i in 0 to loopcnt loop
-            --read rom
-            v_r_nw <= '1';
-            v_io <= (others => 'Z');
             v_addr <= conv_std_logic_vector(16#2000# + i, size14);
+            v_ale <= '1';
+            v_rd_n <= '1';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
             wait for cpu_clk;
 
             --mirror check..
             v_addr <= conv_std_logic_vector(16#2400# + i, size14);
+            v_ale <= '1';
+            v_rd_n <= '1';
             wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
+            wait for cpu_clk;
+
             v_addr <= conv_std_logic_vector(16#2800# + i, size14);
+            v_ale <= '1';
+            v_rd_n <= '1';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
             wait for cpu_clk;
         end loop;
 
         --copy from chr rom to plt tbl.
         for i in 10 to loopcnt + 10 loop
             --read rom
-            v_r_nw <= '1';
-            v_io <= (others => 'Z');
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_wr_n <= '1';
+            v_dff_we_n <= '1';
             v_addr <= conv_std_logic_vector(16#0000# + i, size14);
             wait for cpu_clk;
+            v_dff_we_n <= '0';
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
+            v_wr_n <= '1';
+            wait for cpu_clk;
 
-            --write name tbl #0
+            --write plt tbl #0
+            v_dff_we_n <= '1';
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_wr_n <= '1';
             v_addr <= conv_std_logic_vector(16#3f00# + i, size14);
-            v_io <= v_io;
-            v_r_nw <= '0';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '1';
+            v_wr_n <= '0';
+            v_addr(7 downto 0) <= v_data;
             wait for cpu_clk;
         end loop;
 
         --data check...
+        v_wr_n <= '1';
         for i in 10 to loopcnt + 10 loop
-            --read rom
-            v_r_nw <= '1';
-            v_io <= (others => 'Z');
             v_addr <= conv_std_logic_vector(16#3f00# + i, size14);
+            v_ale <= '1';
+            v_rd_n <= '1';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
             wait for cpu_clk;
 
             --mirror check..
             v_addr <= conv_std_logic_vector(16#3ff0# + i, size14);
+            v_ale <= '1';
+            v_rd_n <= '1';
+            wait for cpu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '0';
             wait for cpu_clk;
         end loop;
+
+        ---read test.
+        ----all data, selctor check.
+        v_wr_n <= '1';
+        for i in 0 to 16#4000# - 1 loop
+            --read rom
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_addr <= conv_std_logic_vector(16#0000# + i, size14);
+            wait for cpu_clk;
+            v_ale <= '0';
+            v_rd_n <= '0';
+            v_addr(size8 - 1 downto 0) <= (others => 'Z');
+            wait for cpu_clk;
+        end loop;
+
         wait;
     end process;