In case if quotient of controller clock rate to device clock rate does
not fit into 4 bit value, choose the maximum acceptable value 0xF, which
stands for 16 clocks.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* slc_tac register definitions
**********************************************************************/
/* Computation of clock cycles on basis of controller and device clock rates */
-#define SLCTAC_CLOCKS(c, n, s) (((1 + (c / n)) & 0xF) << s)
+#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s)
/* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
OSDN Git Service
