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two register machineoperands are not identical unless their subregs match.
author
Chris Lattner
<sabre@nondot.org>
Sun, 30 Dec 2007 20:55:08 +0000
(20:55 +0000)
committer
Chris Lattner
<sabre@nondot.org>
Sun, 30 Dec 2007 20:55:08 +0000
(20:55 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45455
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/CodeGen/MachineInstr.cpp
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diff --git
a/lib/CodeGen/MachineInstr.cpp
b/lib/CodeGen/MachineInstr.cpp
index
f54cbe7
..
e8f692e
100644
(file)
--- a/
lib/CodeGen/MachineInstr.cpp
+++ b/
lib/CodeGen/MachineInstr.cpp
@@
-153,7
+153,8
@@
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
switch (getType()) {
default: assert(0 && "Unrecognized operand type");
case MachineOperand::MO_Register:
- return getReg() == Other.getReg() && isDef() == Other.isDef();
+ return getReg() == Other.getReg() && isDef() == Other.isDef() &&
+ getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
case MachineOperand::MO_MachineBasicBlock: