OSDN Git Service

arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
authorVidya Sagar <vidyas@nvidia.com>
Thu, 5 Sep 2019 10:45:53 +0000 (16:15 +0530)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 20 Sep 2019 19:24:35 +0000 (14:24 -0500)
Add 3.3V and 12V supplies regulators information of x16 PCIe slot in
p2972-0000 platform which is owned by C5 controller and also enable C5
controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

index 62e07e1..4c38426 100644 (file)
                        gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
+
+               vdd_3v3_pcie: regulator@2 {
+                       compatible = "regulator-fixed";
+                       reg = <2>;
+
+                       regulator-name = "PEX_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+                       regulator-boot-on;
+                       enable-active-high;
+               };
+
+               vdd_12v_pcie: regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+
+                       regulator-name = "VDD_12V";
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+                       gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+                       regulator-boot-on;
+                       enable-active-low;
+               };
        };
 };
index 23597d5..d47cd8c 100644 (file)
        };
 
        pcie@141a0000 {
-               status = "disabled";
+               status = "okay";
 
                vddio-pex-ctl-supply = <&vdd_1v8ao>;
+               vpcie3v3-supply = <&vdd_3v3_pcie>;
+               vpcie12v-supply = <&vdd_12v_pcie>;
 
                phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
                       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,