MIPS: Loongson-3: Fix CPU UART irq delivery problem

[ Upstream commit d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea ]

Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
other CPUs) may cause interrupts be lost, especially in multi-package
machines (Package-0's UART irq cannot be delivered to others). So make
mask_loongson_irq() and unmask_loongson_irq() be no-ops.

The original problem (UART IRQ may deliver to any core) is also because
of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to
remove all of the stuff.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20433/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
index 0f75b6b..53424f2 100644 (file)
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -48,45 +48,8 @@ static struct irqaction cascade_irqaction = {
        .name = "cascade",
 };
 
-static inline void mask_loongson_irq(struct irq_data *d)
-{
-       clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
-       irq_disable_hazard();
-
-       /* Workaround: UART IRQ may deliver to any core */
-       if (d->irq == LOONGSON_UART_IRQ) {
-               int cpu = smp_processor_id();
-               int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
-               int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
-               u64 intenclr_addr = smp_group[node_id] |
-                       (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
-               u64 introuter_lpc_addr = smp_group[node_id] |
-                       (u64)(&LOONGSON_INT_ROUTER_LPC);
-
-               *(volatile u32 *)intenclr_addr = 1 << 10;
-               *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
-       }
-}
-
-static inline void unmask_loongson_irq(struct irq_data *d)
-{
-       /* Workaround: UART IRQ may deliver to any core */
-       if (d->irq == LOONGSON_UART_IRQ) {
-               int cpu = smp_processor_id();
-               int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
-               int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
-               u64 intenset_addr = smp_group[node_id] |
-                       (u64)(&LOONGSON_INT_ROUTER_INTENSET);
-               u64 introuter_lpc_addr = smp_group[node_id] |
-                       (u64)(&LOONGSON_INT_ROUTER_LPC);
-
-               *(volatile u32 *)intenset_addr = 1 << 10;
-               *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
-       }
-
-       set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
-       irq_enable_hazard();
-}
+static inline void mask_loongson_irq(struct irq_data *d) { }
+static inline void unmask_loongson_irq(struct irq_data *d) { }
 
  /* For MIPS IRQs which shared by all cores */
 static struct irq_chip loongson_irq_chip = {
@@ -124,7 +87,7 @@ void __init mach_init_irq(void)
        mips_cpu_irq_init();
        init_i8259_irqs();
        irq_set_chip_and_handler(LOONGSON_UART_IRQ,
-                       &loongson_irq_chip, handle_level_irq);
+                       &loongson_irq_chip, handle_percpu_irq);
 
        /* setup HT1 irq */
        setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);